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STGD20N45LZAG

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by adom

STMicroelectronics IGBT Transistors / Modules, DPAK. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs stgd20n45lzag: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain… · Ray 17d ago
viewers stgd20n45lzag: viewers · Ray 22d ago
package.json stgd20n45lzag: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain… · Ray 17d ago
page.json stgd20n45lzag: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain… · Ray 17d ago
README.md Publish 0.1.0 · Ray 22d ago
stgd20n45lzag-etched.glb stgd20n45lzag: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain… · Ray 17d ago
stgd20n45lzag-etched.step stgd20n45lzag: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain… · Ray 17d ago
stgd20n45lzag-hero.glb stgd20n45lzag: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain… · Ray 17d ago
stgd20n45lzag-hero.overlay.json stgd20n45lzag: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain… · Ray 17d ago
stgd20n45lzag.glb Publish 0.1.0 · Ray 22d ago
stgd20n45lzag.kicad_mod Publish 0.1.0 · Ray 22d ago
stgd20n45lzag.kicad_sym Publish 0.1.0 · Ray 22d ago
stgd20n45lzag.lbr Publish 0.1.0 · Ray 22d ago
stgd20n45lzag.step Publish 0.1.0 · Ray 22d ago

STGD20N45LZAG

STMicroelectronics · IGBT Transistors / Modules · DPAK

STGD20N45LZAG from STMicroelectronics, in a DPAK. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate, with an integrated gate-emitter resistor RGE of 11 to 22 kΩ (typ. 16 kΩ) and a gate resistor RG of 120 Ω, and an ESD-protected logic-level gate input; gate-emitter clamped voltage VGE(clamped) is 12 V min. and 16 V typ. at IG = ±2 mA.
2 C passive Collector, internally connected to the TAB; collector-emitter clamped voltage VCES(clamped) is 450 V typ. at IC = 2 mA, VGE = 0 V, with the datasheet giving a 415 V min. and 475 V max. over TJ = -40 °C to 175 °C.
3 E passive Emitter; the emitter-collector breakdown voltage V(BR)ECS is 20 V at IC = 75 mA, VGE = 0 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package DPAK
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: STGD20N45LZAG
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: DPAK (KiCad packages3D, STEP)
  • 3D model files: stgd20n45lzag-etched.step / stgd20n45lzag-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stgd20n45lzag.step / stgd20n45lzag.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (20 pp, sha256 91132ed134f2b9c2, retrieved 2026-10-11, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF