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STGAP1BSTR

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STMicroelectronics Isolators - Gate Drivers, SO-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)stgap1bstrfactory-2.0.0extractor-text

Verified STGAP1BSTR

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 24 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: STGAP1BSTR · SO-24 · 24 pins
  • ✓copper: 24 copper pads, none touching another net
  • ✓datasheet: all 24 pin names found in the 59-page datasheet
  • ✓distributor: lcsc C5267708, digikey 497-STGAP1BSTR-ND, mouser 511-STGAP1BSTR
  • ✓family: SO-24_5.3x15mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-07tz4mmm/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 24 pins = 24 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 24 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ stgap1bstr.kicad_sym✓ stgap1bstr.kicad_mod✓ stgap1bstr.step
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Ray Publish 0.1.0 2674c3d 18h ago

STGAP1BSTR

STMicroelectronics · Isolators - Gate Drivers · SO-24

STGAP1BSTR from STMicroelectronics, in a SO-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Low voltage section ground, referenced for VDD and VREG.
2 SDO output SPI serial data output from the low voltage interface.
3 SDI input SPI serial data input to the device.
4 CS input SPI chip select input, active low.
5 CK input SPI clock input.
6 VREG power_out Internal 3.3 V regulator output and supply pin, absolute maximum -0.30 V to 3.60 V vs GND.
7 VDD power_in Power supply for the low voltage section and internal 3.3 V regulator, absolute maximum -0.30 V to 6.50 V vs GND.
8 IN-/DIAG2 bidirectional Gate command input (inverting) or open drain diagnostic output, selected by DIAG_EN; open drain output voltage limit -0.30 V to 6.50 V.
9 IN+ input Non-inverting gate command input.
10 DIAG1 output Open drain diagnostic output.
11 SD input Shutdown input, active low.
12 GND power_in Low voltage section ground, same net as pin 1.
13 GNDISO power_in High voltage section (isolated) ground, reference for VH, VDESAT, VSENSE and VASC.
14 VL power_in Negative power supply or ground for the high voltage section, range -15 V to 0.30 V vs GNDISO.
15 VREGISO power_out Internal regulator output pin for decoupling of the high voltage section, absolute maximum 3.60 V vs GNDISO.
16 SENSE input Sense input for overcurrent protection, comparator threshold set by SENSEth.
17 VH power_in Positive power supply for the high voltage section, absolute maximum -0.30 V to 40 V vs GNDISO.
18 DESAT bidirectional Desaturation protection pin, analog input/output with voltage limited to VH + 0.30 V vs GNDISO.
19 VCECLAMP input VCE active clamping protection input, voltage limited to VL - 0.30 V to VH + 0.30 V vs VL.
20 GON output Gate source output, drives the gate during turn-on.
21 GOFF output Gate sink output, drives the gate during turn-off.
22 CLAMP output Miller clamp output.
23 VL power_in Negative power supply or ground for the high voltage section, same net as pin 14.
24 ASC input Asynchronous stop command input, voltage limited to -0.30 V to VH + 0.30 V vs GNDISO.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SO-24
Category Power Management (PMIC)
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Low voltage section power supply voltage vs. GND VDD -0.3 6.5 V 5
Low voltage section internal regulator voltage vs. GND VREG -0.3 3.6 V 5
High voltage section internal regulator voltage vs. GNDISO VREGISO -0.3 3.6 V 5
Positive supply voltage (VH vs. GNDISO) VH -0.3 40 V 5
Differential supply voltage (VH vs. VL) VHL -0.3 40 V 5
Negative supply voltage (VL vs. GNDISO) VL -15 0.3 V 5
Open drain output voltage VDIAGx -0.3 6.5 V 5
Open drain DC output current IDIAGx 20 mA VDIAGx < 0.8 V 5
Junction temperature TJ -40 150 °C 5
Storage temperature TS -50 150 °C 5
Ambient temperature TA -40 125 °C 5
Power dissipation input chip PDin 65 mW 5
Common mode transient immunity dVISO/dt 50 V/ns VCM = 1500 V 5
Human body model ESD ESD 2 kV 5
Magnetic field immunity dH/dt 100 A/(m·s) 5
Positive supply voltage (VH vs. GNDISO) VH 4.5 36 V 6
Differential supply voltage (VH vs. VL) VHL 36 V 6
Low voltage section power supply voltage vs. GND VDD 4.5 5.5 V 6
Maximum switching frequency fSW 150 kHz Actual limit depends on power dissipation constraints 6
Input deglitch time tdeglitch 50 70 90 ns INfilter = '11' 7
Input deglitch time tdeglitch 100 160 220 ns INfilter = '01' 7
Input deglitch time tdeglitch 420 500 580 ns INfilter = '10' 7
Minimum propagated input pulse tINmin 20 ns INfilter = '00' and (2LTO_EN = '1' or 2LTOtime = 0x0) 7
Input to output propagation delay ON tDon 90 100 130 ns Deglitch filter and 2LTO disabled 7
Input to output propagation delay OFF tDoff 90 100 130 ns Deglitch filter and 2LTO disabled 7
GON rise time tr 25 ns VL = 0 V; CL = 2 nF, 10% ÷ 90% 7
GOFF rise time tf 25 ns VL = 0V CL = 2 nF, 90% ÷ 10% 7
Pulse width distortion /tDon - tDoff/ PWD 4 10 ns tIN > 100 ns Deglitch filter and 2LTO disabled 7
Deadtime DT 205 250 295 ns DTset = '01' 7
Deadtime DT 650 800 945 ns DTset = '10' 7
Deadtime DT 985 1200 1415 ns DTset = '11' 7
Minimum flag release time trelease 105 μs SD = '0', SD_FLAG = '1' 7
SDO logic 0 output voltage Vol 0.15 V I = 4 mA 7
SDO logic 1 output voltage Voh 4.85 V I = 4 mA 7
INx logic 1 input bias current IINh 55 85 145 μA VIN = 5 V (pin 8 used as IN-) 7
INx logic 0 input bias current IINl 0.1 μA VIN = 0 V (pin 8 used as IN-) 7
SD logic 1 input bias current ISDh 55 85 145 μA VSD = 5 V 7
SD logic 0 input bias current ISDl 0.1 μA VSD = 0 V 7
Input pull-down resistors Rin_pd 35 60 85 kΩ VIN = 5 V (pin 8 used as IN-) 7
CS input pull-up resistor Rin_pu 35 55 80 kΩ CS = GND 7
Source short-circuit current IGON 2.5 A Tpulse < 5 µs, DC = 1%, Tj = -40 to +125 °C 8
Source short-circuit current IGON 5 7 A Tpulse < 5 µs, DC = 1%, Tj = 25 °C 8
Sink short-circuit current IGOFF 2.5 A Tpulse < 5 µs, DC = 1%, Tj = -40 to +125 °C 8
Sink short-circuit current IGOFF 5 6 A Tpulse < 5 µs, DC = 1%, Tj = 25 °C 8
GOFF active clamp SafeClp 3 V IGOFF = 0.2 A; VH floating; GON = GOFF = CLAMP 8
VREG short-circuit current IREG 60 120 mA 0.1 V < VREG < 3.0 V 8
VDD UVLO turn-on threshold VDDon 3.95 4.1 4.3 V 8
VDD UVLO turn-off threshold VDDoff 3.65 3.8 4 V 8
VDD UVLO hysteresis VDDhys 0.15 V 8
VDD OVLO turn-on threshold OVVDDon 5.3 5.5 5.9 V 8
VDD OVLO turn-off threshold OVVDDoff 5.4 5.7 6.1 V 8
VDD OVLO hysteresis OVVDDhys 100 200 300 mV 8
VDD quiescent supply current IQDD 5.2 6.5 7.5 mA VDD = 5 V; SD = 5 V; INx = GND; f = 0 Hz 8
VDD quiescent supply current IQDD 6 8.5 9.5 mA VDD = 5 V; SD = 5 V; fSW = fSW,max 8
VH UVLO turn-on threshold VHon 9.4 10 10.5 V VHONth = '01' 8
VH UVLO turn-on threshold VHon 11.3 12 12.6 V VHONth = '10' 8
VH UVLO turn-on threshold VHon 13.15 14 14.7 V VHONth = '11' 8
VL UVLO turn-on threshold VLon -3.15 -3 -2.8 V VLONth = '01' 8
VDD standby current ISTBY_VDD 0.4 0.8 1 mA VDD = 5 V 12
Thermal resistance junction to ambient Rth(JA) 65 °C/W Mounted on EVALSTGAP1BS rev 2.0 board (two-layer FR4 PCB) 5

CAD (KiCad official)

  • Symbol: STGAP1BSTR
  • Footprint: Package_SO:SO-24_5.3x15mm_P1.27mm
  • 3D model: SO-24 (KiCad packages3D, STEP)
  • 3D model files: stgap1bstr-etched.step / stgap1bstr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stgap1bstr.step / stgap1bstr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (59 pp, sha256 8f7b2ce284230e18, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF