Rev 1: 3 x 5 LED dot matrix

The first attempt. An AI designed a desk nameplate that spells STEVEN in 58 white LEDs, powered from an iPhone charger through a USB-C port on the right edge. It works electrically. It fails as typography: the N reads as an H. That failure is the reason Rev 2 exists.

Rev 1, 3D render of the assembled board
Status Designed and verified in software. Not fabricated.
Date 2026-09-11
Board 98.4 x 26.4 mm, 2 layer FR4, Adom molecule 96x24 nominal, medium machine pins
Letters 58 LEDs, 3 x 5 pixel font, 3.5 mm pixel pitch, 4 mm letter gap, 62 mm of text
Power USB-C on the east edge, 5 V, about 520 mA with every LED lit
Result 0 DRC errors, 62 of 62 nets connected, USB-C geometry inside the guide's reference window
Outcome Superseded by Rev 2. Kept as the record of what was tried first.

The board, live

Orbit, zoom, hover any part for its refdes and net, x-ray the copper with the Nets panel, or run the guided walkthrough. The PCB, Schematic and Parts tabs across the top are live too. Open full screen.

The question this revision asked

Can an AI, given one sentence, produce a manufacturable board that puts a person's name in lights and runs off a phone charger, using the same pipeline (tscircuit, the Adom molecule library, the adom-tsci viewer) that produced earlier Adom nameplates?

The prompt, verbatim, as typed by John Lauer on 2026-09-11:

hey, we want to put Steven's name in lights on a pcb nameplate. put a usbc connector on the right side of the board so he can plug it into his iphone. use adom-tsci and open it in the webview when done.

Method

  1. Template. The AI started from vijay-nameplate, an earlier 3 x 5 LED nameplate on the same stack, and changed the word, the board size and the connector position. The 3 x 5 font came with it unexamined. That inherited assumption is the defect this revision records.
  2. Board size. Six letters at 3 mm pitch need 56 mm of text plus about 13 mm reserved for the USB-C receptacle and its support parts, which does not fit the 80x24 molecule Vijay used. It moved up to 96x24 (98.4 x 26.4 mm real outline).
  3. USB-C. The UsbCReceptacle wrapper was copied byte-for-byte from the adom-usbc guide and placed with mount="east" at pcbX = W/2 - 4 = 44. Two 4.7 kohm CC pulldowns (Rd) make a USB-C charger turn VBUS on. A 100 nF capacitor bypasses VBUS.
  4. Build, then verify geometry, not just DRC. Every build ran tsci build, adom-tsci lint, and a new union-find connectivity check (source/scripts/check-connectivity.py) that follows copper pad to trace to via to pad, layer by layer.
  5. Iterate on layout until the router produced a fully connected board. See Results.

Results

Negative results: the router's silent opens

The first build passed tscircuit's own checks for most nets, yet the board did not work. The autorouter (tscircuit 0.0.1753) sometimes ends a bottom-layer trace directly under a top-layer pad with no via. The trace carries an end_pcb_port_id, so both tscircuit and adom-tsci lint count it as routed. Only the geometric check sees that nothing connects.

Every layout tried, in order:

Layout DRC errors Nets split into islands
3 mm pitch, resistor 1.5 mm below LED (the Vijay layout) 6 3
same, resistors rotated 180 degrees 2 2
3.5 mm pitch, resistor 1.5 mm below 0 1
3.5 mm pitch, resistor 1.75 mm below 0 1
3.5 mm pitch, 1.9 mm / 4.5 mm letter gap / y offset 6.5 (three variants) 0 to 342 1 to 2
router preset auto_cloud n/a 59
router preset sequential_trace build fails on the molecule n/a
3.5 mm pitch, resistor 1.6 mm below, rotated 180 degrees 0 0 (shipped)

The same checker, run against the shipped vijay-nameplate this was copied from, found one real open there too (R24 and R26 isolated from VBUS). That finding was reported, not fixed, since it is a different board.

Final numbers

Check Value
Components 128: 58 LEDs, 60 resistors, 1 capacitor, 1 USB-C, 4 test contacts, 4 machine pins
Routing 186 routed traces for 188 declared (the 2 are the merged same-net USB-C tabs), 78 vias
DRC errors in circuit.json 0
Connectivity 62 of 62 nets, each one island
USB-C pad gap to edge 7.00 mm (guide window 5 to 8)
USB-C anchor hole gap to edge 1.83 mm (guide: more than 0.8)
USB-C mouth overhang 2.31 mm (guide window 2 to 3)
USB-C pads / holes 12 / 6

What went wrong: the N

The N in the 3 x 5 font next to the H from the same font

Three columns give an N nowhere to put its diagonal. The glyph becomes two verticals and a bar near the top, which reads as an H. Seen in the top view, STEVEN reads closer to STEVEH.

Rev 1 top view

Other known gaps, all fixed in Rev 2:

Reproduce this experiment

Tools used

Tool Version What it did here Get it
Claude Code, in Adom's Hydrogen desktop Claude Opus 5 The AI that wrote the board, ran every build and check, and wrote this page Adom Hydrogen
bun 1.4.0 JavaScript runtime that runs tscircuit curl -fsSL https://bun.sh/install | bash
tscircuit, @tscircuit/cli 0.0.1753 / 0.1.1382 Board description in TSX, autorouter, DRC, gerber and GLB export bun install --frozen-lockfile (pinned in bun.lock)
@tsci/adom-inc.molecule, @tsci/adom-inc.library 1.1.15 / 1.1.14 Adom molecule outline and corner machine pins same, through the .npmrc registry npm.tscircuit.com
adom-tsci 1.4.24 Live 3D / PCB / schematic preview, lint, gerber export, walkthrough, the viewer embedded on this page adom-wiki pkg install adom/adom-tsci
adom-usbc guide ships with adom-tsci The USB-C wrapper (copied verbatim) and the edge checks ~/.claude/skills/adom-tsci/guides/adom-usbc.md
scripts/check-connectivity.py this page Geometric pad-trace-via connectivity per net; catches opens DRC misses Python 3 standard library
scripts/sweep.sh this page Parallel layout sweep, reports DRC errors and split nets per variant bash + bun
scripts/make-bom.py this page Real BOM and pick-and-place spliced into the gerber zip Python 3 standard library
glb-datauri-textures.mjs, glb-make-zup.mjs adom-tsci page Makes the 3D models load in the wiki's sandbox and lie flat https://wiki.adom.inc/adom/adom-tsci/render/scripts/
pup (Adom Bridge) The renders on this page, shot in a background browser adom-bridge pup_open_window
adom-wiki Publishing this page preinstalled on Adom containers

What actually ran, in order

  1. Read the adom-tsci and adom-usbc guides, then copied vijay-nameplate (lib, lockfile, node_modules) to a new project and changed the word, board size and connector position.
  2. bunx tsci build lib/index.tsx --glbs --svgs, then read every *_error in circuit.json and ran adom-tsci lint.
  3. Wrote scripts/check-connectivity.py after seeing traces reported as routed that connected nothing, and checked it against a known-good board (bill-nameplate: 0 split).
  4. Swept layouts (the table above) by editing GRID, LETTER_GAP, yOff and the resistor offset, rebuilding each in a scratch copy, until one came back 0 errors and 0 split.
  5. Ran the adom-usbc edge check (pad gap, hole gap, overhang, pad and hole counts).
  6. adom-tsci start . --texture-resolution 2048, checked the console for a USB-C placeholder, compared the served GLB's J1 vertex count with the tscircuit-built one, then took the body-on and body-off USB-C screenshots and read them.
  7. adom-tsci export --format gerbers, then scripts/make-bom.py to replace the empty BOM.

Rebuild it yourself

Everything needed is in rev1/source/. From a Linux or macOS shell with bun installed:

adom-wiki repo download adom/steven-led-nameplate --extract ./steven
cd steven/rev1/source
bun install --frozen-lockfile          # pins tscircuit 0.0.1753, @tscircuit/cli 0.1.1382
bunx tsci build lib/index.tsx --glbs --svgs
python3 scripts/check-connectivity.py  # expect: 62 nets checked, 0 split

Expected: 0 entries whose type ends in _error in dist/lib/index/circuit.json, 186 routed traces. The autorouter is deterministic for a fixed input and fixed package versions; a different tscircuit version routes differently (Rev 2 shows how much).

To preview interactively: adom-tsci start . (Adom's viewer), or open the Rev 1 live viewer on this page.

To fabricate: rev1/fab/gerbers.zip holds copper, mask, silkscreen, paste, outline and drill files plus bom.csv and pick_and_place.csv. Do not fabricate Rev 1; build Rev 2.

Outputs

File What it is License
rev1/source/lib/index.tsx The board, as tscircuit TSX MIT
rev1/source/lib/UsbCReceptacle.tsx USB-C wrapper, verbatim from the adom-usbc guide MIT
rev1/source/scripts/check-connectivity.py Geometric net connectivity check MIT
rev1/source/package.json, bun.lock Exact dependency pins MIT
rev1/viewer/circuit.json Complete circuit description (netlist, placement, routing) CC0
rev1/viewer/3d.glb 3D model, 2048 px board texture CC0
rev1/fab/gerbers.zip Fabrication files CC0
rev1/fab/bom.csv, pick_and_place.csv Assembly data CC0
this document Method, results, negative results CC BY 4.0

Provenance
Requested by John Lauer, Adom Industries (PI, NSF PCL Test Bed node, Fort Worth)
Designed by Claude Opus 5 (Anthropic), running in Claude Code inside Adom's Hydrogen desktop
Toolchain tscircuit 0.0.1753, @tscircuit/cli 0.1.1382, @tsci/adom-inc.molecule 1.1.15, @tsci/adom-inc.library 1.1.14, adom-tsci 1.4.24, bun 1.4.0
Template vijay-nameplate (Adom, 2026-09-11)
Human review John Lauer viewed the live 3D preview and asked for the font change that became Rev 2

Contributor roles (CRediT): John Lauer, conceptualization and supervision. Claude (AI), design, software, validation, writing.

Funding

Adom Industries' electronics prototyping node is funded by the U.S. National Science Foundation Programmable Cloud Laboratories (PCL) Test Bed program (ROR 021nxhr62). This nameplate was made as a worked example of open publishing for the Astera Institute (ROR 00ydx1s47); Astera did not fund it.