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Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	1d ago
viewers	stef01ftr: viewers · Ray	1d ago
package.json	stef01ftr: LCSC part number C2155721 (was published as the bare integer) · Ray	8h ago
page.json	stef01ftr: LCSC part number C2155721 (was published as the bare integer) · Ray	8h ago
README.md	Initial commit: component/stef01ftr · Ray	1d ago
stef01ftr-etched.glb	stef01ftr: factory component page (tier=lcsc) · Ray	1d ago
stef01ftr-etched.step	stef01ftr: factory component page (tier=lcsc) · Ray	1d ago
stef01ftr-hero.glb	Publish 0.1.0 · Ray	1d ago
stef01ftr-hero.overlay.json	Publish 0.1.0 · Ray	1d ago
stef01ftr.glb	Publish 0.1.0 · Ray	1d ago
stef01ftr.kicad_mod	Publish 0.1.0 · Ray	1d ago
stef01ftr.kicad_sym	Publish 0.1.0 · Ray	1d ago
stef01ftr.lbr	Publish 0.1.0 · Ray	1d ago
stef01ftr.step	Publish 0.1.0 · Ray	1d ago

STEF01FTR

STMicroelectronics · Global Sourcing Parts · HTSSOP-14-EP

STEF01FTR from STMicroelectronics, in a HTSSOP-14-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	UVLO	passive	Resistor divider connected between this pin, VCC and GND sets the UVLO threshold; defaults to 14.5 V if left floating.
2	dv/dt	passive	Controls output voltage slew rate at turn-on through internal capacitor (≈3 ms); external capacitor can increase ramp-up time, or pin can be left open if not needed.
3	GND	power_in	Ground pin.
4	Auto	input	Selects thermal protection behavior: latched mode when left floating or connected to voltage >1 V, auto-retry mode when connected to GND.
5	Vclamp	passive	Resistor divider connected between this pin, VOUT and GND sets the overvoltage clamp level; defaults to 28 V if left floating.
6	VOUT	power_out	Output port; all pins must be tied together with short copper tracks.
7	VOUT	power_out	Output port; all pins must be tied together with short copper tracks.
8	VOUT	power_out	Output port; all pins must be tied together with short copper tracks.
9	VOUT	power_out	Output port; all pins must be tied together with short copper tracks.
10	I-Limit	passive	Resistor between this pin and VOUT sets the overload current limit level.
11	Vg	output	Gate driver output for optional external reverse-blocking MOSFET.
12	En/Fault	tri_state	Tri-state bi-directional pin; left floating during normal operation, can be pulled to ground to disable output using open drain/collector, or goes to intermediate state during thermal fault to signal monitoring circuits.
13	PG	output	Open-drain Power Good flag; must be pulled up through external resistor.
14	VCC	power_in	Power supply input port; must be connected to the exposed pad.
15	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	HTSSOP-14-EP
Category	Global Sourcing Parts
Pins	15

CAD (KiCad official)

Symbol: STEF01FTR
Footprint: Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm
3D model: HTSSOP-14-EP (KiCad packages3D, STEP)
3D model files: stef01ftr-etched.step / stef01ftr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stef01ftr.step / stef01ftr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (28 pp, sha256 3da29c01fa2d02a9, retrieved 2026-10-05, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF