component
STEF01FTR
Public Made by Adomby adom
STMicroelectronics Global Sourcing Parts, HTSSOP-14-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+51@@ -0,0 +1,51 @@+# STEF01FTR++**STMicroelectronics** · Global Sourcing Parts · HTSSOP-14-EP++STEF01FTR from STMicroelectronics, in a HTSSOP-14-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | UVLO | passive | Resistor divider connected between this pin, VCC and GND sets the UVLO threshold; defaults to 14.5 V if left floating. |+| 2 | dv/dt | passive | Controls output voltage slew rate at turn-on through internal capacitor (≈3 ms); external capacitor can increase ramp-up time, or pin can be left open if not needed. |+| 3 | GND | power_in | Ground pin. |+| 4 | Auto | input | Selects thermal protection behavior: latched mode when left floating or connected to voltage >1 V, auto-retry mode when connected to GND. |+| 5 | Vclamp | passive | Resistor divider connected between this pin, VOUT and GND sets the overvoltage clamp level; defaults to 28 V if left floating. |+| 6 | VOUT | power_out | Output port; all pins must be tied together with short copper tracks. |+| 7 | VOUT | power_out | Output port; all pins must be tied together with short copper tracks. |+| 8 | VOUT | power_out | Output port; all pins must be tied together with short copper tracks. |+| 9 | VOUT | power_out | Output port; all pins must be tied together with short copper tracks. |+| 10 | I-Limit | passive | Resistor between this pin and VOUT sets the overload current limit level. |+| 11 | Vg | output | Gate driver output for optional external reverse-blocking MOSFET. |+| 12 | En/Fault | tri_state | Tri-state bi-directional pin; left floating during normal operation, can be pulled to ground to disable output using open drain/collector, or goes to intermediate state during thermal fault to signal monitoring circuits. |+| 13 | PG | output | Open-drain Power Good flag; must be pulled up through external resistor. |+| 14 | VCC | power_in | Power supply input port; must be connected to the exposed pad. |+| 15 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | HTSSOP-14-EP |+| Category | Global Sourcing Parts |+| Pins | 15 |++## CAD (KiCad official)++- Symbol: `STEF01FTR`+- Footprint: `Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm`+- 3D model: HTSSOP-14-EP (KiCad packages3D, STEP)+- 3D model files: `stef01ftr-etched.step` / `stef01ftr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stef01ftr.step` / `stef01ftr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589904238546345984) (28 pp, sha256 `3da29c01fa2d02a9`, retrieved 2026-10-05, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/stef01ftr-datasheet.pdf)
page.jsonadded+203@@ -0,0 +1,203 @@+{+ "slug": "stef01ftr",+ "version": "0.1.0",+ "type": "component",+ "description": "STMicroelectronics Global Sourcing Parts, HTSSOP-14-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "global sourcing parts",+ "stef01ftr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "stef01ftr.kicad_sym",+ "stef01ftr.kicad_mod",+ "stef01ftr.glb",+ "stef01ftr.step",+ "stef01ftr.lbr",+ "docs/hero.png",+ "docs/stef01ftr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "stef01ftr-hero.glb",+ "stef01ftr-hero.overlay.json"+ ],+ "component": {+ "mpn": "STEF01FTR",+ "manufacturer": "STMicroelectronics",+ "package": "HTSSOP-14-EP",+ "pin_count": 15,+ "category": "Global Sourcing Parts",+ "subcategory": "Global Sourcing Parts",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589904238546345984",+ "parts": {+ "symbol": "stef01ftr.kicad_sym",+ "footprint": "stef01ftr.kicad_mod",+ "model_3d": "stef01ftr-hero.glb",+ "model_3d_plain": "stef01ftr.glb",+ "model_3d_step": "stef01ftr-etched.step",+ "model_3d_step_plain": "stef01ftr.step",+ "lbr": "stef01ftr.lbr"+ },+ "distributor_links": {+ "lcsc": 2155721,+ "digikey": "497-17779-2-ND",+ "mouser": "511-STEF01FTR"+ },+ "distributor_check": {+ "checked_at": "2026-10-05T23:36:26Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "497-17779-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "511-STEF01FTR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "UVLO",+ "type": "passive",+ "description": "Resistor divider connected between this pin, VCC and GND sets the UVLO threshold; defaults to 14.5 V if left floating."+ },+ {+ "number": "2",+ "name": "dv/dt",+ "type": "passive",+ "description": "Controls output voltage slew rate at turn-on through internal capacitor (≈3 ms); external capacitor can increase ramp-up time, or pin can be left open if not needed."+ },+ {+ "number": "3",+ "name": "GND",+ "type": "power_in",+ "description": "Ground pin."+ },+ {+ "number": "4",+ "name": "Auto",+ "type": "input",+ "description": "Selects thermal protection behavior: latched mode when left floating or connected to voltage >1 V, auto-retry mode when connected to GND."+ },+ {+ "number": "5",+ "name": "Vclamp",+ "type": "passive",+ "description": "Resistor divider connected between this pin, VOUT and GND sets the overvoltage clamp level; defaults to 28 V if left floating."+ },+ {+ "number": "6",+ "name": "VOUT",+ "type": "power_out",+ "description": "Output port; all pins must be tied together with short copper tracks."+ },+ {+ "number": "7",+ "name": "VOUT",+ "type": "power_out",+ "description": "Output port; all pins must be tied together with short copper tracks."+ },+ {+ "number": "8",+ "name": "VOUT",+ "type": "power_out",+ "description": "Output port; all pins must be tied together with short copper tracks."+ },+ {+ "number": "9",+ "name": "VOUT",+ "type": "power_out",+ "description": "Output port; all pins must be tied together with short copper tracks."+ },+ {+ "number": "10",+ "name": "I-Limit",+ "type": "passive",+ "description": "Resistor between this pin and VOUT sets the overload current limit level."+ },+ {+ "number": "11",+ "name": "Vg",+ "type": "output",+ "description": "Gate driver output for optional external reverse-blocking MOSFET."+ },+ {+ "number": "12",+ "name": "En/Fault",+ "type": "tri_state",+ "description": "Tri-state bi-directional pin; left floating during normal operation, can be pulled to ground to disable output using open drain/collector, or goes to intermediate state during thermal fault to signal monitoring circuits."+ },+ {+ "number": "13",+ "name": "PG",+ "type": "output",+ "description": "Open-drain Power Good flag; must be pulled up through external resistor."+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Power supply input port; must be connected to the exposed pad."+ },+ {+ "number": "15",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 15 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 13,+ "cost_usd": 0.0995,+ "at": "2026-10-05T23:36:12"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589904238546345984",+ "pages": 28,+ "sha256": "3da29c01fa2d02a9",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 15,+ "described": 15,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}