component
STD1NK80ZT4
Public Made by Adomby adom
STMicroelectronics MOSFETs, DPAK. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 21h ago |
| viewers | 21h ago |
| package.json | 21h ago |
| page.json | 21h ago |
| README.md | 21h ago |
| std1nk80zt4-etched.glb | 21h ago |
| std1nk80zt4-etched.step | 21h ago |
| std1nk80zt4-hero.glb | 21h ago |
| std1nk80zt4-hero.overlay.json | 21h ago |
| std1nk80zt4.glb | 21h ago |
| std1nk80zt4.kicad_mod | 21h ago |
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| std1nk80zt4.lbr | 21h ago |
| std1nk80zt4.step | 21h ago |
| verification.json | 21h ago |
STD1NK80ZT4
STMicroelectronics · MOSFETs · DPAK
STD1NK80ZT4 from STMicroelectronics, in a DPAK. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate of the Zener-protected N-channel MOSFET, with gate-source voltage limited to ±30 V per Table 1. |
| 2 | D | passive | Drain of the N-channel MOSFET, also connected to the TAB, with drain-source voltage rated at 800 V per Table 1. |
| 3 | S | passive | Source of the N-channel MOSFET, with continuous source-drain current limited to 1 A per Table 7. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | DPAK |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDS | 800 | V | 2 | |||
| Gate-source voltage | VGS | -30 | 30 | V | 2 | ||
| Drain current (continuous) | ID | 1 | A | Drain current (continuous) at TC = 25 °C | 2 | ||
| Drain current (continuous) | ID | 0.63 | A | Drain current (continuous) at TC = 100 °C | 2 | ||
| Drain current (pulsed) | IDM | 5 | A | Pulse width limited by safe operating area | 2 | ||
| Total power dissipation | PTOT | 45 | W | Total power dissipation at TC = 25 °C | 2 | ||
| Gate-source human body model ESD | ESD | 1 | kV | Gate-source human body model (R = 1.5 kΩ, C = 100 pF) | 2 | ||
| Peak diode recovery voltage slope | dv/dt | 4.5 | V/ns | ISD ≤ 1 A, di/dt ≤ 200 A/μs, VDS (peak) ≤ V(BR)DSS, VDD = 80% V(BR)DSS | 2 | ||
| Storage temperature range | Tstg | -55 | 150 | °C | Storage temperature range | 2 | |
| Thermal resistance, junction-to-case | RthJC | 2.78 | °C/W | 2 | |||
| Thermal resistance, junction-to-ambient | RthJA | 50 | °C/W | When mounted on 1 inch² FR-4, 2 Oz copper board | 2 | ||
| Avalanche current, repetitive or not repetitive | IAR | 1 | A | Pulse width limited by TJ max. | 2 | ||
| Single pulse avalanche energy | EAS | 50 | mJ | Starting TJ = 25 °C, ID = IAR, VDD = 50 V | 2 | ||
| Drain-source breakdown voltage | V(BR)DSS | 800 | V | VGS = 0 V, ID = 1 mA | 3 | ||
| Zero gate voltage drain current | IDSS | 1 | µA | VGS = 0 V, VDS = 800 V | 3 | ||
| Zero gate voltage drain current | IDSS | 50 | µA | VGS = 0 V, VDS = 800 V, TC = 125 °C | 3 | ||
| Gate body leakage current | IGSS | -10 | 10 | µA | VDS = 0 V, VGS = ±20 V | 3 | |
| Gate threshold voltage | VGS(th) | 3 | 3.8 | 4.5 | V | VDS = VGS, ID = 50 µA | 3 |
| Static drain-source on-resistance | RDS(on) | 13 | 16 | Ω | VGS = 10 V, ID = 0.5 A | 3 | |
| Source-drain current | ISD | 1 | A | 4 | |||
| Source-drain current (pulsed) | ISDM | 5 | A | 4 | |||
| Forward on voltage | VSD | 1.6 | V | ISD = 1 A, VGS = 0 V | 4 | ||
| Reverse recovery time | trr | 365 | ns | ISD = 1.1 A, di/dt = 100 A/µs, VDD = 50 V | 4 | ||
| Reverse recovery charge | Qrr | 802 | nC | ISD = 1.1 A, di/dt = 100 A/µs, VDD = 50 V | 4 | ||
| Reverse recovery current | IRRM | 4.4 | A | ISD = 1.1 A, di/dt = 100 A/µs, VDD = 50 V | 4 | ||
| Reverse recovery time | trr | 389 | ns | ISD = 1.1 A, di/dt = 100 A/µs, VDD = 50 V, TJ = 150 °C | 4 | ||
| Reverse recovery charge | Qrr | 891 | nC | ISD = 1.1 A, di/dt = 100 A/µs, VDD = 50 V, TJ = 150 °C | 4 | ||
| Reverse recovery current | IRRM | 4.6 | A | ISD = 1.1 A, di/dt = 100 A/µs, VDD = 50 V, TJ = 150 °C | 4 | ||
| Input capacitance | Ciss | 160 | pF | VDS = 25 V, f = 1 MHz, VGS = 0 V | 3 | ||
| Output capacitance | Coss | 26 | pF | VDS = 25 V, f = 1 MHz, VGS = 0 V | 3 | ||
| Reverse transfer capacitance | Crss | 6.7 | pF | VDS = 25 V, f = 1 MHz, VGS = 0 V | 3 | ||
| Equivalent output capacitance | Coss eq. | 9.5 | pF | VGS = 0 V, VDS = 0 to 640 V | 3 | ||
| Total gate charge | Qg | 7.7 | nC | VDD = 640, ID = 1.1 A, VGS = 0 to 10 V | 3 | ||
| Gate-source charge | Qgs | 1.4 | nC | VDD = 640, ID = 1.1 A, VGS = 0 to 10 V | 3 | ||
| Gate-drain charge | Qgd | 4.5 | nC | VDD = 640, ID = 1.1 A, VGS = 0 to 10 V | 3 | ||
| Turn-on delay time | td(on) | 7 | ns | VDD = 400 V, ID = 0.55 A, RG = 4.7 Ω, VGS = 10 V | 3 | ||
| Rise time | tr | 23 | ns | VDD = 400 V, ID = 0.55 A, RG = 4.7 Ω, VGS = 10 V | 3 | ||
| Turn-off delay time | td(off) | 18 | ns | VDD = 400 V, ID = 0.55 A, RG = 4.7 Ω, VGS = 10 V | 3 | ||
| Fall time | tf | 28 | ns | VDD = 400 V, ID = 0.55 A, RG = 4.7 Ω, VGS = 10 V | 3 |
CAD (KiCad official)
- Symbol:
STD1NK80ZT4 - Footprint:
Package_TO_SOT_SMD:TO-252-2 - 3D model: DPAK (KiCad packages3D, STEP)
- 3D model files:
std1nk80zt4-etched.step/std1nk80zt4-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);std1nk80zt4.step/std1nk80zt4.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (15 pp, sha256
458d0636e8f391ae, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).