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STD17NF03LT4

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STMicroelectronics MOSFETs, DPAK. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs std17nf03lt4: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray 23d ago
viewers std17nf03lt4: viewers · Ray 1mo ago
package.json std17nf03lt4: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray 23d ago
page.json std17nf03lt4: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray 23d ago
README.md std17nf03lt4: specified limits as data (metadata.characteristics, 25 rows from the datasheet) · Ray 25d ago
std17nf03lt4-etched.fit.json std17nf03lt4: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
std17nf03lt4-etched.glb std17nf03lt4: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray 23d ago
std17nf03lt4-etched.step std17nf03lt4: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray 23d ago
std17nf03lt4.glb Publish 0.1.0 · Ray 1mo ago
std17nf03lt4.kicad_mod Publish 0.1.0 · Ray 1mo ago
std17nf03lt4.kicad_sym Publish 0.1.0 · Ray 1mo ago
std17nf03lt4.lbr Publish 0.1.0 · Ray 1mo ago
std17nf03lt4.step Publish 0.1.0 · Ray 1mo ago

STD17NF03LT4

STMicroelectronics · MOSFETs · DPAK

STD17NF03LT4 from STMicroelectronics, in a DPAK. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Gate input Gate control input terminal; maximum voltage rating ±16 V with gate threshold voltage of 1 to 2.2 V (VDS = VGS, ID = 250µA).
2 Drain passive Drain terminal; maximum drain-source voltage 30 V (VGS = 0) with continuous current rating of 17 A at 25°C case temperature and 12 A at 100°C case temperature.
3 Source passive Source terminal with integrated body diode rated for continuous source-drain current of 22 A and forward voltage drop of 1.5 V (ISD = 17A, VGS = 0).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package DPAK
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-source voltage (VGS = 0) VDS 30 V VGS = 0 3
Drain-gate voltage VDGR 30 V RGS = 20 kΩ 3
Gate-source voltage VGS -16 16 V 3
Drain current (continuous) at TC = 25°C ID 17 A TC = 25°C 3
Drain current (continuous) at TC = 100°C ID 12 A TC = 100°C 3
Drain current (pulsed) IDM 68 A Pulse width limited by safe operating area 3
Total dissipation at TC = 25°C Ptot 30 W TC = 25°C 3
Derating factor 0.2 W/°C 3
Peak diode recovery avalanche energy dv/dt 7 V/ns ISD ≤17A, di/dt ≤300A/µs, VDD =V(BR)DSS, Tj ≤ TJMAX 3
Single pulse avalanche energy EAS 200 mJ Starting Tj = 25 °C, ID = 8.5A, VDD = 15V 3
Storage temperature Tstg -55 175 °C 3
Thermal resistance junction-case max Rthj-case 5 °C/W 3
Thermal resistance junction-to ambient max Rthj-amb 100 °C/W 3
Maximum lead temperature for soldering purpose TJ 275 °C 3
Drain-source breakdown voltage V(BR)DSS 30 V ID = 250µA, VGS = 0 4
Zero gate voltage drain current (VGS = 0) IDSS 1 µA VDS = Max rating 4
Zero gate voltage drain current (VGS = 0) IDSS 10 µA VDS = Max rating, TC = 125°C 4
Gate-body leakage current IGSS -100 100 nA VDS = 0, VGS = ± 16V 4
Gate threshold voltage VGS(th) 1 1.5 2.2 V VDS = VGS, ID = 250µA 4
Static drain-source on resistance RDS(on) 0.038 0.05 Ω VGS = 10V, ID = 8.5A 4
Static drain-source on resistance RDS(on) 0.045 0.06 Ω VGS = 5V, ID = 8.5A 4
Total gate charge Qg 4.8 6.5 nC VDD = 3024V, ID = 17A, VGS = 5V, RG = 4.7Ω (see Figure 14) 4
Source-drain current ISD 22 A 5
Source-drain current (pulsed) ISDM 88 A 5
Forward on voltage VSD 1.5 V ISD = 17A, VGS = 0 5

CAD (KiCad official)

  • Symbol: STD17NF03LT4
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: DPAK (KiCad packages3D, STEP)
  • 3D model files: std17nf03lt4-etched.step / std17nf03lt4-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); std17nf03lt4.step / std17nf03lt4.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (14 pp, sha256 6dc44ff5ca24c198, retrieved 2026-09-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF