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STC90C516AD-40I-LQFP44
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STC Micro Microcontrollers (MCU/MPU/SOC), LQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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STC90C516AD-40I-LQFP44
STC Micro · Microcontrollers (MCU/MPU/SOC) · LQFP-44(10x10)
STC90C516AD-40I-LQFP44 from STC Micro, in a LQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.5 | bidirectional | Standard quasi-bidirectional I/O port pin PORT1[5]; no alternate function is listed for this pin in the LQFP44 table. |
| 2 | P1.6 | bidirectional | Standard quasi-bidirectional I/O port pin PORT1[6]; no alternate function is listed for this pin in the LQFP44 table. |
| 3 | P1.7 | bidirectional | Standard quasi-bidirectional I/O port pin PORT1[7]; no alternate function is listed for this pin in the LQFP44 table. |
| 4 | RST | input | Reset pin: holding it high for at least 24 clock cycles plus 10 µs puts the MCU into reset, and it starts from 0000H when pulled back low. |
| 5 | P3.0/RxD | bidirectional | Standard I/O port pin PORT3[0]; serves as RxD, the serial port 1 data receive input. |
| 6 | P4.3/INT2 | bidirectional | Standard I/O port pin PORT4[3]; serves as external interrupt 2 input (falling-edge or low-level triggered). |
| 7 | P3.1/TxD | bidirectional | Standard I/O port pin PORT3[1]; serves as TxD, the serial port 1 data transmit output. |
| 8 | P3.2/INT0 | bidirectional | Standard I/O port pin PORT3[2]; serves as external interrupt 0 input, falling-edge or low-level triggered. |
| 9 | P3.3/INT1 | bidirectional | Standard I/O port pin PORT3[3]; serves as external interrupt 1 input, falling-edge or low-level triggered. |
| 10 | P3.4/T0 | bidirectional | Standard I/O port pin PORT3[4]; serves as external count input to Timer/Counter 0. |
| 11 | P3.5/T1 | bidirectional | Standard I/O port pin PORT3[5]; serves as external count input to Timer/Counter 1. |
| 12 | P3.6/WR | bidirectional | Standard I/O port pin PORT3[6]; serves as WR, the external data memory write strobe. |
| 13 | P3.7/RD | bidirectional | Standard I/O port pin PORT3[7]; serves as RD, the external data memory read strobe. |
| 14 | XTAL2 | output | Output of the internal clock inverting amplifier for the external crystal; may be left floating when an external clock drives XTAL1. |
| 15 | XTAL1 | input | Input to the internal clock inverting amplifier for the external crystal; acts as the external clock input when an external clock source is used directly. |
| 16 | Gnd | power_in | Power supply negative terminal (ground). |
| 17 | P4.0 | bidirectional | Standard I/O port pin PORT4[0] (Port 4 is bit-addressable at SFR address E8H). |
| 18 | P2.0 | bidirectional | Port 2 bit 0 with internal pull-up; I/O pin, or low-order high address bit A8 when external memory is used. |
| 19 | P2.1 | bidirectional | Port 2 bit 1 with internal pull-up; I/O pin, or address bit A9 when external memory is used. |
| 20 | P2.2 | bidirectional | Port 2 bit 2 with internal pull-up; I/O pin, or address bit A10 when external memory is used. |
| 21 | P2.3 | bidirectional | Port 2 bit 3 with internal pull-up; I/O pin, or address bit A11 when external memory is used. |
| 22 | P2.4 | bidirectional | Port 2 bit 4 with internal pull-up; I/O pin, or address bit A12 when external memory is used. |
| 23 | P2.5 | bidirectional | Port 2 bit 5 with internal pull-up; I/O pin, or address bit A13 when external memory is used. |
| 24 | P2.6 | bidirectional | Port 2 bit 6 with internal pull-up; I/O pin, or address bit A14 when external memory is used. |
| 25 | P2.7 | bidirectional | Port 2 bit 7 with internal pull-up; I/O pin, or high-order address bit A15 when external memory is used. |
| 26 | P4.4/PSEN | bidirectional | Standard I/O port pin PORT4[4]; labelled PSEN on the pinout diagram, with no further function described in the pin table. |
| 27 | P4.5/ALE | bidirectional | ALE address latch enable output by default; can be set to standard I/O P4.5 in the ISP programmer, and also serves as programming pulse input. |
| 28 | P4.1 | bidirectional | Standard I/O port pin PORT4[1]. |
| 29 | P4.6/EA | bidirectional | Standard I/O port pin PORT4[6]; labelled EA on the pinout diagram, with no further function described in the pin table. |
| 30 | P0.7 | bidirectional | Port 0 bit 7, open-drain after power-on reset; needs an external 10K-4.7K pull-up when used as I/O, and is the multiplexed data/address bus line AD7 when used as bus. |
| 31 | P0.6 | bidirectional | Port 0 bit 6, open-drain after power-on reset; needs an external 10K-4.7K pull-up when used as I/O, and is the multiplexed bus line AD6 when used as bus. |
| 32 | P0.5 | bidirectional | Port 0 bit 5, open-drain after power-on reset; needs an external 10K-4.7K pull-up when used as I/O, and is the multiplexed bus line AD5 when used as bus. |
| 33 | P0.4 | bidirectional | Port 0 bit 4, open-drain after power-on reset; needs an external 10K-4.7K pull-up when used as I/O, and is the multiplexed bus line AD4 when used as bus. |
| 34 | P0.3 | bidirectional | Port 0 bit 3, open-drain after power-on reset; needs an external 10K-4.7K pull-up when used as I/O, and is the multiplexed bus line AD3 when used as bus. |
| 35 | P0.2 | bidirectional | Port 0 bit 2, open-drain after power-on reset; needs an external 10K-4.7K pull-up when used as I/O, and is the multiplexed bus line AD2 when used as bus. |
| 36 | P0.1 | bidirectional | Port 0 bit 1, open-drain after power-on reset; needs an external 10K-4.7K pull-up when used as I/O, and is the multiplexed bus line AD1 when used as bus. |
| 37 | P0.0 | bidirectional | Port 0 bit 0, open-drain after power-on reset; needs an external 10K-4.7K pull-up when used as I/O, and is the multiplexed bus line AD0 when used as bus. |
| 38 | Vcc | power_in | Power supply positive terminal. |
| 39 | P4.2/INT3 | bidirectional | Standard I/O port pin PORT4[2]; serves as external interrupt 3 input, falling-edge or low-level triggered. |
| 40 | P1.0/T2 | bidirectional | Standard I/O port pin PORT1[0]; serves as external input to Timer/Counter 2. |
| 41 | P1.1/T2EX | bidirectional | Standard I/O port pin PORT1[1]; serves as T2EX, the Timer/Counter 2 capture/reload trigger control input. |
| 42 | P1.2 | bidirectional | Standard I/O port pin PORT1[2]; no alternate function is listed for this pin in the LQFP44 table. |
| 43 | P1.3 | bidirectional | Standard I/O port pin PORT1[3]; no alternate function is listed for this pin in the LQFP44 table. |
| 44 | P1.4 | bidirectional | Standard I/O port pin PORT1[4]; no alternate function is listed for this pin in the LQFP44 table. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STC Micro |
| Package | LQFP-44(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 44 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature | TST | -55 | 125 | ℃ | 431 | ||
| Operating temperature (I) | TA | -40 | 85 | ℃ | 431 | ||
| DC power supply (5V) | VDD - VSS | -0.3 | 6 | V | 431 | ||
| Voltage on any pin | -0.5 | 5.5 | V | 431 | |||
| Operating Voltage | VDD | 3.8 | 5 | 5.5 | V | 431 | |
| Operating Current | ICC | 4 | 20 | mA | 5V | 431 | |
| Input Low (P0,P1,P2,P3, P4) | VIL1 | 0.8 | V | 5V | 431 | ||
| Input Low voltage (RESET, XTAL1) | VIL2 | 1.5 | V | 5V | 431 | ||
| Input High (P0,P1,P2,P3, P4, /EA) | VIH1 | 2 | V | 5V | 431 | ||
| Input High (RESET) | VIH2 | 3 | V | 5V | 431 | ||
| Sinking Current for output low (P1,P2,P3,P4) | IOL1 | 4 | 6 | mA | 5V | 431 | |
| Sinking Current for output low (P0,ALE,PSEN) | IOL2 | 8 | 12 | mA | 5V | 431 | |
| Sourcing Current for output high (P1,P2,P3,P4) | IOH1 | 150 | 220 | uA | 5V | 431 | |
| Sourcing Current for output high (ALE,PSEN) | IOH2 | 14 | 20 | mA | 5V | 431 | |
| Logic 0 input current (P1,P2,P3,P4) | IIL | 18 | 50 | uA | Vpin=0V | 431 | |
| Logic 1 to 0 transition current (P1,P2,P3,P4) | ITL | 270 | 600 | uA | Vpin=2.0V | 431 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the | 138 |
CAD (KiCad official)
- Symbol:
STC90C516AD-40I-LQFP44 - Footprint:
Package_QFP:LQFP-44_10x10mm_P0.8mm - 3D model: LQFP-44(10x10) (KiCad packages3D, STEP)
- 3D model files:
stc90c516ad-40i-lqfp44-etched.step/stc90c516ad-40i-lqfp44-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stc90c516ad-40i-lqfp44.step/stc90c516ad-40i-lqfp44.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STC Micro datasheet (502 pp, sha256
1875b8d4226f5c42, retrieved 2026-10-20, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# STC90C516AD-40I-LQFP44
**STC Micro** · Microcontrollers (MCU/MPU/SOC) · LQFP-44(10x10)
STC90C516AD-40I-LQFP44 from STC Micro, in a LQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.5 | bidirectional | Standard quasi-bidirectional I/O port pin PORT1[5]; no alternate function is listed for this pin in the LQFP44 table. |
| 2 | P1.6 | bidirectional | Standard quasi-bidirectional I/O port pin PORT1[6]; no alternate function is listed for this pin in the LQFP44 table. |
| 3 | P1.7 | bidirectional | Standard quasi-bidirectional I/O port pin PORT1[7]; no alternate function is listed for this pin in the LQFP44 table. |
| 4 | RST | input | Reset pin: holding it high for at least 24 clock cycles plus 10 µs puts the MCU into reset, and it starts from 0000H when pulled back low. |
| 5 | P3.0/RxD | bidirectional | Standard I/O port pin PORT3[0]; serves as RxD, the serial port 1 data receive input. |
| 6 | P4.3/INT2 | bidirectional | Standard I/O port pin PORT4[3]; serves as external interrupt 2 input (falling-edge or low-level triggered). |
| 7 | P3.1/TxD | bidirectional | Standard I/O port pin PORT3[1]; serves as TxD, the serial port 1 data transmit output. |
| 8 | P3.2/INT0 | bidirectional | Standard I/O port pin PORT3[2]; serves as external interrupt 0 input, falling-edge or low-level triggered. |
| 9 | P3.3/INT1 | bidirectional | Standard I/O port pin PORT3[3]; serves as external interrupt 1 input, falling-edge or low-level triggered. |
| 10 | P3.4/T0 | bidirectional | Standard I/O port pin PORT3[4]; serves as external count input to Timer/Counter 0. |
| 11 | P3.5/T1 | bidirectional | Standard I/O port pin PORT3[5]; serves as external count input to Timer/Counter 1. |
| 12 | P3.6/WR | bidirectional | Standard I/O port pin PORT3[6]; serves as WR, the external data memory write strobe. |
| 13 | P3.7/RD | bidirectional | Standard I/O port pin PORT3[7]; serves as RD, the external data memory read strobe. |
| 14 | XTAL2 | output | Output of the internal clock inverting amplifier for the external crystal; may be left floating when an external clock drives XTAL1. |
| 15 | XTAL1 | input | Input to the internal clock inverting amplifier for the external crystal; acts as the external clock input when an external clock source is used directly. |
| 16 | Gnd | power_in | Power supply negative terminal (ground). |
| 17 | P4.0 | bidirectional | Standard I/O port pin PORT4[0] (Port 4 is bit-addressable at SFR address E8H). |
| 18 | P2.0 | bidirectional | Port 2 bit 0 with internal pull-up; I/O pin, or low-order high address bit A8 when external memory is used. |
| 19 | P2.1 | bidirectional | Port 2 bit 1 with internal pull-up; I/O pin, or address bit A9 when external memory is used. |
| 20 | P2.2 | bidirectional | Port 2 bit 2 with internal pull-up; I/O pin, or address bit A10 when external memory is used. |
| 21 | P2.3 | bidirectional | Port 2 bit 3 with internal pull-up; I/O pin, or address bit A11 when external memory is used. |
| 22 | P2.4 | bidirectional | Port 2 bit 4 with internal pull-up; I/O pin, or address bit A12 when external memory is used. |
| 23 | P2.5 | bidirectional | Port 2 bit 5 with internal pull-up; I/O pin, or address bit A13 when external memory is used. |
| 24 | P2.6 | bidirectional | Port 2 bit 6 with internal pull-up; I/O pin, or address bit A14 when external memory is used. |
| 25 | P2.7 | bidirectional | Port 2 bit 7 with internal pull-up; I/O pin, or high-order address bit A15 when external memory is used. |
| 26 | P4.4/PSEN | bidirectional | Standard I/O port pin PORT4[4]; labelled PSEN on the pinout diagram, with no further function described in the pin table. |
| 27 | P4.5/ALE | bidirectional | ALE address latch enable output by default; can be set to standard I/O P4.5 in the ISP programmer, and also serves as programming pulse input. |
| 28 | P4.1 | bidirectional | Standard I/O port pin PORT4[1]. |
| 29 | P4.6/EA | bidirectional | Standard I/O port pin PORT4[6]; labelled EA on the pinout diagram, with no further function described in the pin table. |
| 30 | P0.7 | bidirectional | Port 0 bit 7, open-drain after power-on reset; needs an external 10K-4.7K pull-up when used as I/O, and is the multiplexed data/address bus line AD7 when used as bus. |
| 31 | P0.6 | bidirectional | Port 0 bit 6, open-drain after power-on reset; needs an external 10K-4.7K pull-up when used as I/O, and is the multiplexed bus line AD6 when used as bus. |
| 32 | P0.5 | bidirectional | Port 0 bit 5, open-drain after power-on reset; needs an external 10K-4.7K pull-up when used as I/O, and is the multiplexed bus line AD5 when used as bus. |
| 33 | P0.4 | bidirectional | Port 0 bit 4, open-drain after power-on reset; needs an external 10K-4.7K pull-up when used as I/O, and is the multiplexed bus line AD4 when used as bus. |
| 34 | P0.3 | bidirectional | Port 0 bit 3, open-drain after power-on reset; needs an external 10K-4.7K pull-up when used as I/O, and is the multiplexed bus line AD3 when used as bus. |
| 35 | P0.2 | bidirectional | Port 0 bit 2, open-drain after power-on reset; needs an external 10K-4.7K pull-up when used as I/O, and is the multiplexed bus line AD2 when used as bus. |
| 36 | P0.1 | bidirectional | Port 0 bit 1, open-drain after power-on reset; needs an external 10K-4.7K pull-up when used as I/O, and is the multiplexed bus line AD1 when used as bus. |
| 37 | P0.0 | bidirectional | Port 0 bit 0, open-drain after power-on reset; needs an external 10K-4.7K pull-up when used as I/O, and is the multiplexed bus line AD0 when used as bus. |
| 38 | Vcc | power_in | Power supply positive terminal. |
| 39 | P4.2/INT3 | bidirectional | Standard I/O port pin PORT4[2]; serves as external interrupt 3 input, falling-edge or low-level triggered. |
| 40 | P1.0/T2 | bidirectional | Standard I/O port pin PORT1[0]; serves as external input to Timer/Counter 2. |
| 41 | P1.1/T2EX | bidirectional | Standard I/O port pin PORT1[1]; serves as T2EX, the Timer/Counter 2 capture/reload trigger control input. |
| 42 | P1.2 | bidirectional | Standard I/O port pin PORT1[2]; no alternate function is listed for this pin in the LQFP44 table. |
| 43 | P1.3 | bidirectional | Standard I/O port pin PORT1[3]; no alternate function is listed for this pin in the LQFP44 table. |
| 44 | P1.4 | bidirectional | Standard I/O port pin PORT1[4]; no alternate function is listed for this pin in the LQFP44 table. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STC Micro |
| Package | LQFP-44(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 44 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature | TST | -55 | | 125 | ℃ | | 431 |
| Operating temperature (I) | TA | -40 | | 85 | ℃ | | 431 |
| DC power supply (5V) | VDD - VSS | -0.3 | | 6 | V | | 431 |
| Voltage on any pin | | -0.5 | | 5.5 | V | | 431 |
| Operating Voltage | VDD | 3.8 | 5 | 5.5 | V | | 431 |
| Operating Current | ICC | | 4 | 20 | mA | 5V | 431 |
| Input Low (P0,P1,P2,P3, P4) | VIL1 | | | 0.8 | V | 5V | 431 |
| Input Low voltage (RESET, XTAL1) | VIL2 | | | 1.5 | V | 5V | 431 |
| Input High (P0,P1,P2,P3, P4, /EA) | VIH1 | 2 | | | V | 5V | 431 |
| Input High (RESET) | VIH2 | 3 | | | V | 5V | 431 |
| Sinking Current for output low (P1,P2,P3,P4) | IOL1 | 4 | 6 | | mA | 5V | 431 |
| Sinking Current for output low (P0,ALE,PSEN) | IOL2 | 8 | 12 | | mA | 5V | 431 |
| Sourcing Current for output high (P1,P2,P3,P4) | IOH1 | 150 | 220 | | uA | 5V | 431 |
| Sourcing Current for output high (ALE,PSEN) | IOH2 | 14 | 20 | | mA | 5V | 431 |
| Logic 0 input current (P1,P2,P3,P4) | IIL | | 18 | 50 | uA | Vpin=0V | 431 |
| Logic 1 to 0 transition current (P1,P2,P3,P4) | ITL | | 270 | 600 | uA | Vpin=2.0V | 431 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | | Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the | 138 |
## CAD (KiCad official)
- Symbol: `STC90C516AD-40I-LQFP44`
- Footprint: `Package_QFP:LQFP-44_10x10mm_P0.8mm`
- 3D model: LQFP-44(10x10) (KiCad packages3D, STEP)
- 3D model files: `stc90c516ad-40i-lqfp44-etched.step` / `stc90c516ad-40i-lqfp44-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stc90c516ad-40i-lqfp44.step` / `stc90c516ad-40i-lqfp44.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STC Micro datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586172911534792704) (502 pp, sha256 `1875b8d4226f5c42`, retrieved 2026-10-20, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/stc90c516ad-40i-lqfp44-datasheet.pdf)