component
STC8C2K64S4-36I-LQFP44
Public Made by Adomby adom
STC Micro Microcontroller Units (MCUs/MPUs/SOCs), LQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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STC8C2K64S4-36I-LQFP44
STC Micro · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-44(10x10)
STC8C2K64S4-36I-LQFP44 from STC Micro, in a LQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.0 | bidirectional | Standard I/O port P1.0, also RxD2 (UART2 receive pin); input-only function when used as UART receive, port is high-impedance input after power-on. |
| 2 | P1.1 | bidirectional | Standard I/O port P1.1, also TxD2 (UART2 transmit output). |
| 3 | P1.2 | bidirectional | Standard I/O port P1.2, also SS (SPI slave select), T2 (Timer 2 external clock input). |
| 4 | P1.3 | bidirectional | Standard I/O port P1.3, also MOSI (SPI master out/slave in) and T2CLKO (Timer 2 clock output). |
| 5 | P1.4 | bidirectional | Standard I/O port P1.4, also MISO (SPI master in/slave out) and I2C data line SDA. |
| 6 | P4.4 | bidirectional | Standard I/O port P4.4, also RD (external bus read strobe) and TxD_4 (UART1 transmit alternate). |
| 7 | P1.5 | bidirectional | Standard I/O port P1.5, also SPI clock SCLK and I2C clock SCL. |
| 8 | P1.6 | bidirectional | Standard I/O port P1.6, also RxD_3 (UART1 receive alternate), XTALO (external crystal output) and MCLKO_2 (main clock output); high-impedance input when used as external clock input pin. |
| 9 | P1.7 | bidirectional | Standard I/O port P1.7, also TxD_3 (UART1 transmit alternate) and XTALI (external crystal/clock input). |
| 10 | P4.5 | bidirectional | Standard I/O port P4.5 with full I/O function, configurable in four modes. |
| 11 | P4.6 | bidirectional | Standard I/O port P4.6 with full I/O function, configurable in four modes. |
| 12 | P4.7 | bidirectional | Standard I/O port P4.7 with full I/O function, configurable in four modes. |
| 13 | P5.4 | bidirectional | Standard I/O port P5.4, also RST (active-low reset input when configured as reset pin) and MCLKO (main clock output); powers up with internal 4K pull-up active for about 6.5 ms. |
| 14 | Vcc | power_in | Power supply pin; operating voltage 1.9V to 5.5V. |
| 15 | P5.5 | bidirectional | Standard I/O port P5.5. |
| 16 | Gnd | power_in | Ground pin. |
| 17 | P4.0 | bidirectional | Standard I/O port P4.0, also WR_3 (external bus write strobe alternate) and RxD2_2 (UART2 receive alternate). |
| 18 | P3.0 | bidirectional | Standard I/O port P3.0, also RxD (UART1 receive) and INT4 (external interrupt 4); weak pull-up after power-on and used with P3.1 for USB download mode detection. |
| 19 | P3.1 | bidirectional | Standard I/O port P3.1, also TxD (UART1 transmit); weak pull-up after power-on, must not be held low together with P3.0 and P3.2 at power-up unless USB ISP is intended. |
| 20 | P3.2 | bidirectional | Standard I/O port P3.2, also INT0 (external interrupt 0), SCLK_4 and I2C clock SCL_4; high-impedance input after power-on. |
| 21 | P3.3 | bidirectional | Standard I/O port P3.3, also INT1 (external interrupt 1), MISO_4 and I2C data SDA_4. |
| 22 | P3.4 | bidirectional | Standard I/O port P3.4, also T0 (Timer 0 external clock input), T1CLKO, MOSI_4 and CMPO (comparator output). |
| 23 | P3.5 | bidirectional | Standard I/O port P3.5, also T1 (Timer 1 external clock input), T0CLKO and SS_4 (SPI slave select). |
| 24 | P3.6 | bidirectional | Standard I/O port P3.6, also INT2 (external interrupt 2), WR_2 (external bus write), RxD_2 and CMP- (comparator negative input). |
| 25 | P4.1 | bidirectional | Standard I/O port P4.1, also ALE (address latch enable) and CMPO_2 (comparator output alternate). |
| 26 | P2.0 | bidirectional | Standard I/O port P2.0, also A8 (external bus address bit 8). |
| 27 | P4.2 | bidirectional | Standard I/O port P4.2, also RD_3 (external bus read alternate) and TxD2_2 (UART2 transmit alternate). |
| 28 | P2.1 | bidirectional | Standard I/O port P2.1, also A9 (external bus address bit 9). |
| 29 | P2.2 | bidirectional | Standard I/O port P2.2, also A10 (external bus address bit 10) and SS_2 (SPI slave select alternate). |
| 30 | P2.3 | bidirectional | Standard I/O port P2.3, also A11 (external bus address bit 11) and MOSI_2 (SPI alternate). |
| 31 | P2.4 | bidirectional | Standard I/O port P2.4, also A12 (external bus address bit 12), MISO_2 and I2C data SDA_2. |
| 32 | P2.5 | bidirectional | Standard I/O port P2.5, also A13 (external bus address bit 13), SCLK_2 and I2C clock SCL_2. |
| 33 | P2.6 | bidirectional | Standard I/O port P2.6, also A14 (external bus address bit 14). |
| 34 | P2.7 | bidirectional | Standard I/O port P2.7, also A15 (external bus address bit 15). |
| 35 | P0.0 | bidirectional | Standard I/O port P0.0, also AD0 (multiplexed address/data bus bit 0) and RxD3 (UART3 receive). |
| 36 | P0.1 | bidirectional | Standard I/O port P0.1, also AD1 (multiplexed address/data bus bit 1) and TxD3 (UART3 transmit). |
| 37 | P0.2 | bidirectional | Standard I/O port P0.2, also AD2 (multiplexed address/data bus bit 2) and RxD4 (UART4 receive). |
| 38 | P4.3 | bidirectional | Standard I/O port P4.3, also WR (external bus write strobe) and RxD_4 (UART1 receive alternate). |
| 39 | P0.3 | bidirectional | Standard I/O port P0.3, also AD3 (multiplexed address/data bus bit 3) and TxD4 (UART4 transmit). |
| 40 | P0.4 | bidirectional | Standard I/O port P0.4, also AD4 (multiplexed address/data bus bit 4) and T3 (Timer 3 external clock input). |
| 41 | P0.5 | bidirectional | Standard I/O port P0.5, also AD5 (multiplexed address/data bus bit 5) and T3CLKO (Timer 3 clock output). |
| 42 | P0.6 | bidirectional | Standard I/O port P0.6, also AD6 (multiplexed address/data bus bit 6) and T4 (Timer 4 external clock input). |
| 43 | P0.7 | bidirectional | Standard I/O port P0.7, also AD7 (multiplexed address/data bus bit 7) and T4CLKO (Timer 4 clock output). |
| 44 | P1.0 | bidirectional | Standard I/O port P1.0, also RxD2 (UART2 receive pin). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STC Micro |
| Package | LQFP-44(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 44 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature | -55 | 150 | ℃ | 786 | |||
| Operating temperature | -40 | 85 | ℃ | 786 | |||
| Operating voltage | 1.9 | 5.5 | V | 786 | |||
| VDD to ground voltage | VDD | -0.3 | 5.5 | V | 786 | ||
| I/O port to ground voltage | -0.3 | V | max VDD+0.3 | 786 | |||
| Logic 1 to 0 transition current | ITL | 100 | 270 | 600 | uA | 端口电压 2.0V | 787 |
| I/O pull-up resistor | RPU | 5.8 | 5.9 | 6 | KΩ | 787 | |
| Input low voltage (Schmitt trigger on) | VIL1 | 0.99 | V | 打开施密特触发 | 787 | ||
| Input low voltage (Schmitt trigger off) | VIL1 | 1.07 | V | 关闭施密特触发 | 787 | ||
| Input high voltage, normal I/O (Schmitt trigger on) | VIH1 | 1.18 | V | 打开施密特触发 | 787 | ||
| Input high voltage, normal I/O (Schmitt trigger off) | VIH1 | 1.09 | V | 关闭施密特触发 | 787 | ||
| Input high voltage, reset pin | VIH2 | 1.18 | 0.99 | V | 787 | ||
| Logic 0 input current | IIL | 50 | uA | 端口电压 0V | 787 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the following | 419 |
CAD (KiCad official)
- Symbol:
STC8C2K64S4-36I-LQFP44 - Footprint:
Package_QFP:LQFP-44_10x10mm_P0.8mm - 3D model: LQFP-44(10x10) (KiCad packages3D, STEP)
- 3D model files:
stc8c2k64s4-36i-lqfp44-etched.step/stc8c2k64s4-36i-lqfp44-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stc8c2k64s4-36i-lqfp44.step/stc8c2k64s4-36i-lqfp44.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STC Micro datasheet (956 pp, sha256
f8fa5bab02998432, retrieved 2026-10-27, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# STC8C2K64S4-36I-LQFP44
**STC Micro** · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-44(10x10)
STC8C2K64S4-36I-LQFP44 from STC Micro, in a LQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.0 | bidirectional | Standard I/O port P1.0, also RxD2 (UART2 receive pin); input-only function when used as UART receive, port is high-impedance input after power-on. |
| 2 | P1.1 | bidirectional | Standard I/O port P1.1, also TxD2 (UART2 transmit output). |
| 3 | P1.2 | bidirectional | Standard I/O port P1.2, also SS (SPI slave select), T2 (Timer 2 external clock input). |
| 4 | P1.3 | bidirectional | Standard I/O port P1.3, also MOSI (SPI master out/slave in) and T2CLKO (Timer 2 clock output). |
| 5 | P1.4 | bidirectional | Standard I/O port P1.4, also MISO (SPI master in/slave out) and I2C data line SDA. |
| 6 | P4.4 | bidirectional | Standard I/O port P4.4, also RD (external bus read strobe) and TxD_4 (UART1 transmit alternate). |
| 7 | P1.5 | bidirectional | Standard I/O port P1.5, also SPI clock SCLK and I2C clock SCL. |
| 8 | P1.6 | bidirectional | Standard I/O port P1.6, also RxD_3 (UART1 receive alternate), XTALO (external crystal output) and MCLKO_2 (main clock output); high-impedance input when used as external clock input pin. |
| 9 | P1.7 | bidirectional | Standard I/O port P1.7, also TxD_3 (UART1 transmit alternate) and XTALI (external crystal/clock input). |
| 10 | P4.5 | bidirectional | Standard I/O port P4.5 with full I/O function, configurable in four modes. |
| 11 | P4.6 | bidirectional | Standard I/O port P4.6 with full I/O function, configurable in four modes. |
| 12 | P4.7 | bidirectional | Standard I/O port P4.7 with full I/O function, configurable in four modes. |
| 13 | P5.4 | bidirectional | Standard I/O port P5.4, also RST (active-low reset input when configured as reset pin) and MCLKO (main clock output); powers up with internal 4K pull-up active for about 6.5 ms. |
| 14 | Vcc | power_in | Power supply pin; operating voltage 1.9V to 5.5V. |
| 15 | P5.5 | bidirectional | Standard I/O port P5.5. |
| 16 | Gnd | power_in | Ground pin. |
| 17 | P4.0 | bidirectional | Standard I/O port P4.0, also WR_3 (external bus write strobe alternate) and RxD2_2 (UART2 receive alternate). |
| 18 | P3.0 | bidirectional | Standard I/O port P3.0, also RxD (UART1 receive) and INT4 (external interrupt 4); weak pull-up after power-on and used with P3.1 for USB download mode detection. |
| 19 | P3.1 | bidirectional | Standard I/O port P3.1, also TxD (UART1 transmit); weak pull-up after power-on, must not be held low together with P3.0 and P3.2 at power-up unless USB ISP is intended. |
| 20 | P3.2 | bidirectional | Standard I/O port P3.2, also INT0 (external interrupt 0), SCLK_4 and I2C clock SCL_4; high-impedance input after power-on. |
| 21 | P3.3 | bidirectional | Standard I/O port P3.3, also INT1 (external interrupt 1), MISO_4 and I2C data SDA_4. |
| 22 | P3.4 | bidirectional | Standard I/O port P3.4, also T0 (Timer 0 external clock input), T1CLKO, MOSI_4 and CMPO (comparator output). |
| 23 | P3.5 | bidirectional | Standard I/O port P3.5, also T1 (Timer 1 external clock input), T0CLKO and SS_4 (SPI slave select). |
| 24 | P3.6 | bidirectional | Standard I/O port P3.6, also INT2 (external interrupt 2), WR_2 (external bus write), RxD_2 and CMP- (comparator negative input). |
| 25 | P4.1 | bidirectional | Standard I/O port P4.1, also ALE (address latch enable) and CMPO_2 (comparator output alternate). |
| 26 | P2.0 | bidirectional | Standard I/O port P2.0, also A8 (external bus address bit 8). |
| 27 | P4.2 | bidirectional | Standard I/O port P4.2, also RD_3 (external bus read alternate) and TxD2_2 (UART2 transmit alternate). |
| 28 | P2.1 | bidirectional | Standard I/O port P2.1, also A9 (external bus address bit 9). |
| 29 | P2.2 | bidirectional | Standard I/O port P2.2, also A10 (external bus address bit 10) and SS_2 (SPI slave select alternate). |
| 30 | P2.3 | bidirectional | Standard I/O port P2.3, also A11 (external bus address bit 11) and MOSI_2 (SPI alternate). |
| 31 | P2.4 | bidirectional | Standard I/O port P2.4, also A12 (external bus address bit 12), MISO_2 and I2C data SDA_2. |
| 32 | P2.5 | bidirectional | Standard I/O port P2.5, also A13 (external bus address bit 13), SCLK_2 and I2C clock SCL_2. |
| 33 | P2.6 | bidirectional | Standard I/O port P2.6, also A14 (external bus address bit 14). |
| 34 | P2.7 | bidirectional | Standard I/O port P2.7, also A15 (external bus address bit 15). |
| 35 | P0.0 | bidirectional | Standard I/O port P0.0, also AD0 (multiplexed address/data bus bit 0) and RxD3 (UART3 receive). |
| 36 | P0.1 | bidirectional | Standard I/O port P0.1, also AD1 (multiplexed address/data bus bit 1) and TxD3 (UART3 transmit). |
| 37 | P0.2 | bidirectional | Standard I/O port P0.2, also AD2 (multiplexed address/data bus bit 2) and RxD4 (UART4 receive). |
| 38 | P4.3 | bidirectional | Standard I/O port P4.3, also WR (external bus write strobe) and RxD_4 (UART1 receive alternate). |
| 39 | P0.3 | bidirectional | Standard I/O port P0.3, also AD3 (multiplexed address/data bus bit 3) and TxD4 (UART4 transmit). |
| 40 | P0.4 | bidirectional | Standard I/O port P0.4, also AD4 (multiplexed address/data bus bit 4) and T3 (Timer 3 external clock input). |
| 41 | P0.5 | bidirectional | Standard I/O port P0.5, also AD5 (multiplexed address/data bus bit 5) and T3CLKO (Timer 3 clock output). |
| 42 | P0.6 | bidirectional | Standard I/O port P0.6, also AD6 (multiplexed address/data bus bit 6) and T4 (Timer 4 external clock input). |
| 43 | P0.7 | bidirectional | Standard I/O port P0.7, also AD7 (multiplexed address/data bus bit 7) and T4CLKO (Timer 4 clock output). |
| 44 | P1.0 | bidirectional | Standard I/O port P1.0, also RxD2 (UART2 receive pin). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STC Micro |
| Package | LQFP-44(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 44 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature | | -55 | | 150 | ℃ | | 786 |
| Operating temperature | | -40 | | 85 | ℃ | | 786 |
| Operating voltage | | 1.9 | | 5.5 | V | | 786 |
| VDD to ground voltage | VDD | -0.3 | | 5.5 | V | | 786 |
| I/O port to ground voltage | | -0.3 | | | V | max VDD+0.3 | 786 |
| Logic 1 to 0 transition current | ITL | 100 | 270 | 600 | uA | 端口电压 2.0V | 787 |
| I/O pull-up resistor | RPU | 5.8 | 5.9 | 6 | KΩ | | 787 |
| Input low voltage (Schmitt trigger on) | VIL1 | | | 0.99 | V | 打开施密特触发 | 787 |
| Input low voltage (Schmitt trigger off) | VIL1 | | | 1.07 | V | 关闭施密特触发 | 787 |
| Input high voltage, normal I/O (Schmitt trigger on) | VIH1 | 1.18 | | | V | 打开施密特触发 | 787 |
| Input high voltage, normal I/O (Schmitt trigger off) | VIH1 | 1.09 | | | V | 关闭施密特触发 | 787 |
| Input high voltage, reset pin | VIH2 | 1.18 | | 0.99 | V | | 787 |
| Logic 0 input current | IIL | | | 50 | uA | 端口电压 0V | 787 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | | Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the following | 419 |
## CAD (KiCad official)
- Symbol: `STC8C2K64S4-36I-LQFP44`
- Footprint: `Package_QFP:LQFP-44_10x10mm_P0.8mm`
- 3D model: LQFP-44(10x10) (KiCad packages3D, STEP)
- 3D model files: `stc8c2k64s4-36i-lqfp44-etched.step` / `stc8c2k64s4-36i-lqfp44-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stc8c2k64s4-36i-lqfp44.step` / `stc8c2k64s4-36i-lqfp44.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STC Micro datasheet](docs/stc8c2k64s4-36i-lqfp44-datasheet.pdf) (956 pp, sha256 `f8fa5bab02998432`, retrieved 2026-10-27, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/stc8c2k64s4-36i-lqfp44-datasheet.pdf)