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STC89C58RD+40I-PDIP40
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STC Micro Microcontroller Units (MCUs/MPUs/SOCs), DIP-40. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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STC89C58RD+40I-PDIP40
STC Micro · Microcontroller Units (MCUs/MPUs/SOCs) · DIP-40
STC89C58RD+40I-PDIP40 from STC Micro, in a DIP-40. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | T2/P1.0 | bidirectional | P1.0 is a standard quasi-bidirectional I/O (PORT1[0]) that also serves as the Timer/Counter 2 external input T2. |
| 2 | T2EX/P1.1 | bidirectional | P1.1 is a standard I/O (PORT1[1]) that also serves as T2EX, the Timer 2 capture/reload trigger input. |
| 3 | P1.2 | bidirectional | P1.2 is a standard quasi-bidirectional I/O (PORT1[2]) with weak pull-up after reset. |
| 4 | P1.3 | bidirectional | P1.3 is a standard quasi-bidirectional I/O (PORT1[3]) with weak pull-up after reset. |
| 5 | P1.4 | bidirectional | P1.4 is a standard quasi-bidirectional I/O (PORT1[4]) with weak pull-up after reset. |
| 6 | P1.5 | bidirectional | P1.5 is a standard quasi-bidirectional I/O (PORT1[5]) with weak pull-up after reset. |
| 7 | P1.6 | bidirectional | P1.6 is a standard quasi-bidirectional I/O (PORT1[6]) with weak pull-up after reset. |
| 8 | P1.7 | bidirectional | P1.7 is a standard quasi-bidirectional I/O (PORT1[7]) with weak pull-up after reset. |
| 9 | RST | input | Reset input: holding RST high for at least 24 clock cycles plus 10us resets the MCU, which then starts at address 0000H after RST returns low. |
| 10 | RxD/P3.0 | bidirectional | P3.0 is a standard I/O (PORT3[0]) that also serves as the UART1 serial receive input RxD. |
| 11 | TxD/P3.1 | bidirectional | P3.1 is a standard I/O (PORT3[1]) that also serves as the UART1 serial transmit output TxD. |
| 12 | INT0/P3.2 | bidirectional | P3.2 is a standard I/O (PORT3[2]) that also serves as external interrupt 0 input INT0, selectable as falling-edge or low-level triggered. |
| 13 | INT1/P3.3 | bidirectional | P3.3 is a standard I/O (PORT3[3]) that also serves as external interrupt 1 input INT1, selectable as falling-edge or low-level triggered. |
| 14 | T0/P3.4 | bidirectional | P3.4 is a standard I/O (PORT3[4]) that also serves as the Timer/Counter 0 external input T0. |
| 15 | T1/P3.5 | bidirectional | P3.5 is a standard I/O (PORT3[5]) that also serves as the Timer/Counter 1 external input T1. |
| 16 | WR/P3.6 | bidirectional | P3.6 is a standard I/O (PORT3[6]) that also serves as the external data memory write strobe WR. |
| 17 | RD/P3.7 | bidirectional | P3.7 is a standard I/O (PORT3[7]) that also serves as the external data memory read strobe RD. |
| 18 | XTAL2 | output | Output of the internal clock inverting amplifier for the external crystal; when an external clock is applied to XTAL1, this pin may be left floating. |
| 19 | XTAL1 | input | Input of the internal clock inverting amplifier for the external crystal, or the input for an external clock source. |
| 20 | Gnd | power_in | Ground (negative power supply) connection. |
| 21 | P2.0/A8 | bidirectional | P2.0 is a quasi-bidirectional I/O with internal pull-up that also drives address bit A8 when external memory is accessed. |
| 22 | P2.1/A9 | bidirectional | P2.1 is a quasi-bidirectional I/O with internal pull-up that also drives address bit A9 when external memory is accessed. |
| 23 | P2.2/A10 | bidirectional | P2.2 is a quasi-bidirectional I/O with internal pull-up that also drives address bit A10 when external memory is accessed. |
| 24 | P2.3/A11 | bidirectional | P2.3 is a quasi-bidirectional I/O with internal pull-up that also drives address bit A11 when external memory is accessed. |
| 25 | P2.4/A12 | bidirectional | P2.4 is a quasi-bidirectional I/O with internal pull-up that also drives address bit A12 when external memory is accessed. |
| 26 | P2.5/A13 | bidirectional | P2.5 is a quasi-bidirectional I/O with internal pull-up that also drives address bit A13 when external memory is accessed. |
| 27 | P2.6/A14 | bidirectional | P2.6 is a quasi-bidirectional I/O with internal pull-up that also drives address bit A14 when external memory is accessed. |
| 28 | P2.7/A15 | bidirectional | P2.7 is a quasi-bidirectional I/O with internal pull-up that also drives address bit A15 when external memory is accessed. |
| 29 | P4.4/PSEN | bidirectional | On the 90C version this pin is standard I/O P4.4; on the HD version it is PSEN, the external program memory read strobe output. |
| 30 | P4.5/ALE | bidirectional | On the 90C version this pin is P4.5 and defaults to ALE; on the HD version it is ALE, the address latch enable output (also the programming pulse input). |
| 31 | P4.6/EA | input | On the 90C version this pin is standard I/O P4.6; on the HD version it is EA, the internal/external memory select input, which is internally pulled up to Vcc. |
| 32 | P0.7/AD7 | bidirectional | P0.7 is open-drain after reset and needs a 10K-4.7K pull-up when used as I/O, and carries data/address bit AD7 on the multiplexed bus without an external pull-up. |
| 33 | P0.6/AD6 | bidirectional | P0.6 is open-drain after reset and needs a 10K-4.7K pull-up when used as I/O, and carries data/address bit AD6 on the multiplexed bus without an external pull-up. |
| 34 | P0.5/AD5 | bidirectional | P0.5 is open-drain after reset and needs a 10K-4.7K pull-up when used as I/O, and carries data/address bit AD5 on the multiplexed bus without an external pull-up. |
| 35 | P0.4/AD4 | bidirectional | P0.4 is open-drain after reset and needs a 10K-4.7K pull-up when used as I/O, and carries data/address bit AD4 on the multiplexed bus without an external pull-up. |
| 36 | P0.3/AD3 | bidirectional | P0.3 is open-drain after reset and needs a 10K-4.7K pull-up when used as I/O, and carries data/address bit AD3 on the multiplexed bus without an external pull-up. |
| 37 | P0.2/AD2 | bidirectional | P0.2 is open-drain after reset and needs a 10K-4.7K pull-up when used as I/O, and carries data/address bit AD2 on the multiplexed bus without an external pull-up. |
| 38 | P0.1/AD1 | bidirectional | P0.1 is open-drain after reset and needs a 10K-4.7K pull-up when used as I/O, and carries data/address bit AD1 on the multiplexed bus without an external pull-up. |
| 39 | P0.0/AD0 | bidirectional | P0.0 is open-drain after reset and needs a 10K-4.7K pull-up when used as I/O, and carries data/address bit AD0 on the multiplexed bus without an external pull-up. |
| 40 | Vcc | power_in | Positive power supply connection. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STC Micro |
| Package | DIP-40 |
| Category | Embedded Processors & Controllers |
| Pins | 40 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the following | 320 |
CAD (KiCad official)
- Symbol:
STC89C58RD+40I-PDIP40 - Footprint:
Package_DIP:DIP-40_W25.4mm - 3D model: DIP-40 (KiCad packages3D, STEP)
- 3D model files:
stc89c58rd-40i-pdip40-etched.step/stc89c58rd-40i-pdip40-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stc89c58rd-40i-pdip40.step/stc89c58rd-40i-pdip40.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STC Micro datasheet (1691 pp, sha256
fac7be430b93e2dd, retrieved 2026-10-27, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# STC89C58RD+40I-PDIP40
**STC Micro** · Microcontroller Units (MCUs/MPUs/SOCs) · DIP-40
STC89C58RD+40I-PDIP40 from STC Micro, in a DIP-40. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | T2/P1.0 | bidirectional | P1.0 is a standard quasi-bidirectional I/O (PORT1[0]) that also serves as the Timer/Counter 2 external input T2. |
| 2 | T2EX/P1.1 | bidirectional | P1.1 is a standard I/O (PORT1[1]) that also serves as T2EX, the Timer 2 capture/reload trigger input. |
| 3 | P1.2 | bidirectional | P1.2 is a standard quasi-bidirectional I/O (PORT1[2]) with weak pull-up after reset. |
| 4 | P1.3 | bidirectional | P1.3 is a standard quasi-bidirectional I/O (PORT1[3]) with weak pull-up after reset. |
| 5 | P1.4 | bidirectional | P1.4 is a standard quasi-bidirectional I/O (PORT1[4]) with weak pull-up after reset. |
| 6 | P1.5 | bidirectional | P1.5 is a standard quasi-bidirectional I/O (PORT1[5]) with weak pull-up after reset. |
| 7 | P1.6 | bidirectional | P1.6 is a standard quasi-bidirectional I/O (PORT1[6]) with weak pull-up after reset. |
| 8 | P1.7 | bidirectional | P1.7 is a standard quasi-bidirectional I/O (PORT1[7]) with weak pull-up after reset. |
| 9 | RST | input | Reset input: holding RST high for at least 24 clock cycles plus 10us resets the MCU, which then starts at address 0000H after RST returns low. |
| 10 | RxD/P3.0 | bidirectional | P3.0 is a standard I/O (PORT3[0]) that also serves as the UART1 serial receive input RxD. |
| 11 | TxD/P3.1 | bidirectional | P3.1 is a standard I/O (PORT3[1]) that also serves as the UART1 serial transmit output TxD. |
| 12 | INT0/P3.2 | bidirectional | P3.2 is a standard I/O (PORT3[2]) that also serves as external interrupt 0 input INT0, selectable as falling-edge or low-level triggered. |
| 13 | INT1/P3.3 | bidirectional | P3.3 is a standard I/O (PORT3[3]) that also serves as external interrupt 1 input INT1, selectable as falling-edge or low-level triggered. |
| 14 | T0/P3.4 | bidirectional | P3.4 is a standard I/O (PORT3[4]) that also serves as the Timer/Counter 0 external input T0. |
| 15 | T1/P3.5 | bidirectional | P3.5 is a standard I/O (PORT3[5]) that also serves as the Timer/Counter 1 external input T1. |
| 16 | WR/P3.6 | bidirectional | P3.6 is a standard I/O (PORT3[6]) that also serves as the external data memory write strobe WR. |
| 17 | RD/P3.7 | bidirectional | P3.7 is a standard I/O (PORT3[7]) that also serves as the external data memory read strobe RD. |
| 18 | XTAL2 | output | Output of the internal clock inverting amplifier for the external crystal; when an external clock is applied to XTAL1, this pin may be left floating. |
| 19 | XTAL1 | input | Input of the internal clock inverting amplifier for the external crystal, or the input for an external clock source. |
| 20 | Gnd | power_in | Ground (negative power supply) connection. |
| 21 | P2.0/A8 | bidirectional | P2.0 is a quasi-bidirectional I/O with internal pull-up that also drives address bit A8 when external memory is accessed. |
| 22 | P2.1/A9 | bidirectional | P2.1 is a quasi-bidirectional I/O with internal pull-up that also drives address bit A9 when external memory is accessed. |
| 23 | P2.2/A10 | bidirectional | P2.2 is a quasi-bidirectional I/O with internal pull-up that also drives address bit A10 when external memory is accessed. |
| 24 | P2.3/A11 | bidirectional | P2.3 is a quasi-bidirectional I/O with internal pull-up that also drives address bit A11 when external memory is accessed. |
| 25 | P2.4/A12 | bidirectional | P2.4 is a quasi-bidirectional I/O with internal pull-up that also drives address bit A12 when external memory is accessed. |
| 26 | P2.5/A13 | bidirectional | P2.5 is a quasi-bidirectional I/O with internal pull-up that also drives address bit A13 when external memory is accessed. |
| 27 | P2.6/A14 | bidirectional | P2.6 is a quasi-bidirectional I/O with internal pull-up that also drives address bit A14 when external memory is accessed. |
| 28 | P2.7/A15 | bidirectional | P2.7 is a quasi-bidirectional I/O with internal pull-up that also drives address bit A15 when external memory is accessed. |
| 29 | P4.4/PSEN | bidirectional | On the 90C version this pin is standard I/O P4.4; on the HD version it is PSEN, the external program memory read strobe output. |
| 30 | P4.5/ALE | bidirectional | On the 90C version this pin is P4.5 and defaults to ALE; on the HD version it is ALE, the address latch enable output (also the programming pulse input). |
| 31 | P4.6/EA | input | On the 90C version this pin is standard I/O P4.6; on the HD version it is EA, the internal/external memory select input, which is internally pulled up to Vcc. |
| 32 | P0.7/AD7 | bidirectional | P0.7 is open-drain after reset and needs a 10K-4.7K pull-up when used as I/O, and carries data/address bit AD7 on the multiplexed bus without an external pull-up. |
| 33 | P0.6/AD6 | bidirectional | P0.6 is open-drain after reset and needs a 10K-4.7K pull-up when used as I/O, and carries data/address bit AD6 on the multiplexed bus without an external pull-up. |
| 34 | P0.5/AD5 | bidirectional | P0.5 is open-drain after reset and needs a 10K-4.7K pull-up when used as I/O, and carries data/address bit AD5 on the multiplexed bus without an external pull-up. |
| 35 | P0.4/AD4 | bidirectional | P0.4 is open-drain after reset and needs a 10K-4.7K pull-up when used as I/O, and carries data/address bit AD4 on the multiplexed bus without an external pull-up. |
| 36 | P0.3/AD3 | bidirectional | P0.3 is open-drain after reset and needs a 10K-4.7K pull-up when used as I/O, and carries data/address bit AD3 on the multiplexed bus without an external pull-up. |
| 37 | P0.2/AD2 | bidirectional | P0.2 is open-drain after reset and needs a 10K-4.7K pull-up when used as I/O, and carries data/address bit AD2 on the multiplexed bus without an external pull-up. |
| 38 | P0.1/AD1 | bidirectional | P0.1 is open-drain after reset and needs a 10K-4.7K pull-up when used as I/O, and carries data/address bit AD1 on the multiplexed bus without an external pull-up. |
| 39 | P0.0/AD0 | bidirectional | P0.0 is open-drain after reset and needs a 10K-4.7K pull-up when used as I/O, and carries data/address bit AD0 on the multiplexed bus without an external pull-up. |
| 40 | Vcc | power_in | Positive power supply connection. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STC Micro |
| Package | DIP-40 |
| Category | Embedded Processors & Controllers |
| Pins | 40 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | | Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the following | 320 |
## CAD (KiCad official)
- Symbol: `STC89C58RD+40I-PDIP40`
- Footprint: `Package_DIP:DIP-40_W25.4mm`
- 3D model: DIP-40 (KiCad packages3D, STEP)
- 3D model files: `stc89c58rd-40i-pdip40-etched.step` / `stc89c58rd-40i-pdip40-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stc89c58rd-40i-pdip40.step` / `stc89c58rd-40i-pdip40.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STC Micro datasheet](docs/stc89c58rd-40i-pdip40-datasheet.pdf) (1691 pp, sha256 `fac7be430b93e2dd`, retrieved 2026-10-27, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/stc89c58rd-40i-pdip40-datasheet.pdf)