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STC89C516RD+40I-PDIP40
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STC Micro Microcontrollers (MCU/MPU/SOC), DIP-40. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownSTC89C516RD+40I-PDIP40
STC Micro · Microcontrollers (MCU/MPU/SOC) · DIP-40
STC89C516RD+40I-PDIP40 from STC Micro, in a DIP-40. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.0/T2 | bidirectional | Standard I/O port bit P1.0, quasi-bidirectional with weak pull-up after power-on reset; also the external input of Timer/Counter 2 (T2). |
| 2 | P1.1/T2EX | bidirectional | Standard I/O port bit P1.1; also T2EX, the Timer 2 capture/reload trigger input. |
| 3 | P1.2 | bidirectional | Standard I/O port bit P1.2 (PORT1[2]), quasi-bidirectional with weak pull-up after power-on reset. |
| 4 | P1.3 | bidirectional | Standard I/O port bit P1.3 (PORT1[3]), quasi-bidirectional with weak pull-up after power-on reset. |
| 5 | P1.4 | bidirectional | Standard I/O port bit P1.4 (PORT1[4]), quasi-bidirectional with weak pull-up after power-on reset. |
| 6 | P1.5 | bidirectional | Standard I/O port bit P1.5 (PORT1[5]), quasi-bidirectional with weak pull-up after power-on reset. |
| 7 | P1.6 | bidirectional | Standard I/O port bit P1.6 (PORT1[6]), quasi-bidirectional with weak pull-up after power-on reset. |
| 8 | P1.7 | bidirectional | Standard I/O port bit P1.7 (PORT1[7]), quasi-bidirectional with weak pull-up after power-on reset. |
| 9 | RST | input | Reset pin; holding RST high for at least 24 clock cycles plus 10 us places the MCU in reset. |
| 10 | RxD/P3.0 | bidirectional | Standard I/O port bit P3.0; also RxD, the serial port 1 receive data input. |
| 11 | TxD/P3.1 | bidirectional | Standard I/O port bit P3.1; also TxD, the serial port 1 transmit data output. |
| 12 | INT0/P3.2 | bidirectional | Standard I/O port bit P3.2; also INT0, external interrupt 0 (falling-edge or low-level triggered). |
| 13 | INT1/P3.3 | bidirectional | Standard I/O port bit P3.3; also INT1, external interrupt 1 (falling-edge or low-level triggered). |
| 14 | T0/P3.4 | bidirectional | Standard I/O port bit P3.4; also T0, the external input of Timer/Counter 0. |
| 15 | T1/P3.5 | bidirectional | Standard I/O port bit P3.5; also T1, the external input of Timer/Counter 1. |
| 16 | WR/P3.6 | bidirectional | Standard I/O port bit P3.6; also WR, the external data memory write strobe output. |
| 17 | RD/P3.7 | bidirectional | Standard I/O port bit P3.7; also RD, the external data memory read strobe output. |
| 18 | XTAL2 | output | Output of the internal inverting oscillator amplifier for the external crystal; left floating when an external clock is driven into XTAL1. |
| 19 | XTAL1 | input | Input to the internal inverting oscillator amplifier, connected to one crystal pin; it is the clock input when an external clock source is used. |
| 20 | Gnd | power_in | Power supply negative terminal, connected to ground. |
| 21 | P2.0/A8 | bidirectional | Port 2 bit P2.0 with internal pull-up; drives address line A8 of the high address byte when external memory is used. |
| 22 | P2.1/A9 | bidirectional | Port 2 bit P2.1 with internal pull-up; drives address line A9 when external memory is used. |
| 23 | P2.2/A10 | bidirectional | Port 2 bit P2.2 with internal pull-up; drives address line A10 when external memory is used. |
| 24 | P2.3/A11 | bidirectional | Port 2 bit P2.3 with internal pull-up; drives address line A11 when external memory is used. |
| 25 | P2.4/A12 | bidirectional | Port 2 bit P2.4 with internal pull-up; drives address line A12 when external memory is used. |
| 26 | P2.5/A13 | bidirectional | Port 2 bit P2.5 with internal pull-up; drives address line A13 when external memory is used. |
| 27 | P2.6/A14 | bidirectional | Port 2 bit P2.6 with internal pull-up; drives address line A14 when external memory is used. |
| 28 | P2.7/A15 | bidirectional | Port 2 bit P2.7 with internal pull-up; drives address line A15 when external memory is used. |
| 29 | P4.4/PSEN | bidirectional | Port 4 bit P4.4 (90C version) or the PSEN external program memory select strobe output (HD version); the pin function depends on the version. |
| 30 | P4.5/ALE | bidirectional | Port 4 bit P4.5 (90C version, ALE default function must be changed in AiCube-ISP) or the ALE address latch enable output (HD version); the function depends on the version. |
| 31 | P4.6/EA | bidirectional | Port 4 bit P4.6 (90C version) or the EA internal/external memory select input (HD version); the function depends on the version. |
| 32 | P0.7/AD7 | bidirectional | Port 0 bit P0.7: open-drain after reset and needs a 10K-4.7K pull-up when used as I/O; multiplexed as data/address bit AD7 without an external pull-up. |
| 33 | P0.6/AD6 | bidirectional | Port 0 bit P0.6: open-drain after reset and needs a 10K-4.7K pull-up when used as I/O; multiplexed as data/address bit AD6 without an external pull-up. |
| 34 | P0.5/AD5 | bidirectional | Port 0 bit P0.5: open-drain after reset and needs a 10K-4.7K pull-up when used as I/O; multiplexed as data/address bit AD5 without an external pull-up. |
| 35 | P0.4/AD4 | bidirectional | Port 0 bit P0.4: open-drain after reset and needs a 10K-4.7K pull-up when used as I/O; multiplexed as data/address bit AD4 without an external pull-up. |
| 36 | P0.3/AD3 | bidirectional | Port 0 bit P0.3: open-drain after reset and needs a 10K-4.7K pull-up when used as I/O; multiplexed as data/address bit AD3 without an external pull-up. |
| 37 | P0.2/AD2 | bidirectional | Port 0 bit P0.2: open-drain after reset and needs a 10K-4.7K pull-up when used as I/O; multiplexed as data/address bit AD2 without an external pull-up. |
| 38 | P0.1/AD1 | bidirectional | Port 0 bit P0.1: open-drain after reset and needs a 10K-4.7K pull-up when used as I/O; multiplexed as data/address bit AD1 without an external pull-up. |
| 39 | P0.0/AD0 | bidirectional | Port 0 bit P0.0: open-drain after reset and needs a 10K-4.7K pull-up when used as I/O; multiplexed as data/address bit AD0 without an external pull-up. |
| 40 | Vcc | power_in | Power supply positive terminal; the 5V C-suffix part is specified for 5.5 V to 3.3 V operation in the selection table. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STC Micro |
| Package | DIP-40 |
| Category | Embedded Processors & Controllers |
| Pins | 40 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC power supply (5V) VDD - VSS | VDD - VSS | -0.3 | 6 | V | 1658 | ||
| Voltage on any pin | -0.5 | 5.5 | V | 1658 | |||
| Storage temperature | TST | -55 | 125 | ℃ | 1658 | ||
| Operating temperature (I) | TA | -40 | 85 | ℃ | Industrial grade (I) | 1658 | |
| VDD Operating Voltage (5V MCU) | VDD | 3.8 | 5 | 5.5 | V | 1658 | |
| Operating Current | ICC | 4 | 20 | mA | 5V | 1658 | |
| Input Low (P0,P1,P2,P3,P4) | VIL1 | 0.8 | V | 5V | 1658 | ||
| Input Low voltage (RESET, XTAL1) | VIL2 | 1.5 | V | 5V | 1658 | ||
| Input High (P0,P1,P2,P3,P4, /EA) | VIH1 | 2 | V | 5V | 1658 | ||
| Input High (RESET) | VIH2 | 3 | V | 5V | 1658 | ||
| Sinking Current for output low (P1,P2,P3,P4) | IOL1 | 4 | 6 | mA | 5V | 1658 | |
| Sinking Current for output low (P0,ALE,PSEN) | IOL2 | 8 | 12 | mA | 5V | 1658 | |
| Sourcing Current for output high (P1,P2,P3,P4) | IOH1 | 150 | 220 | uA | 5V | 1658 | |
| Sourcing Current for output high (ALE,PSEN) | IOH2 | 14 | 20 | mA | 5V | 1658 | |
| Logic 0 input current (P1,P2,P3,P4) | IIL | 18 | 50 | uA | Vpin=0V | 1658 | |
| Logic 1 to 0 transition current (P1,P2,P3,P4) | ITL | 270 | 600 | uA | Vpin=2.0V | 1658 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the following | 320 |
CAD (KiCad official)
- Symbol:
STC89C516RD+40I-PDIP40 - Footprint:
Package_DIP:DIP-40_W25.4mm - 3D model: DIP-40 (KiCad packages3D, STEP)
- 3D model files:
stc89c516rd-40i-pdip40-etched.step/stc89c516rd-40i-pdip40-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stc89c516rd-40i-pdip40.step/stc89c516rd-40i-pdip40.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STC Micro datasheet (1691 pp, sha256
fac7be430b93e2dd, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).