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STC32G12K128-35I-QFN48

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STC Micro Microcontrollers (MCU/MPU/SOC), QFN-48(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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STC32G12K128-35I-QFN48

STC Micro · Microcontrollers (MCU/MPU/SOC) · QFN-48(6x6)

STC32G12K128-35I-QFN48 from STC Micro, in a QFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P5.3 bidirectional Standard I/O port pin, also serial 4 TxD4_2, CAN2_TX_2 and LIN_TX_2 outputs; port is high-impedance input after power-on until its mode is set.
2 P0.5 bidirectional Standard I/O port pin, also address/data bus AD5, ADC channel 13 input, and Timer 3 clock-divided output T3CLKO; high-impedance input after power-on until mode is set.
3 P0.6 bidirectional Standard I/O port pin, also address/data bus AD6, ADC channel 14 input, Timer 4 external clock input T4 and enhanced PWM fault input PWMFLT2_2.
4 P0.7 bidirectional Standard I/O port pin, also address/data bus AD7 and Timer 4 clock-divided output T4CLKO; high-impedance input after power-on until mode is set.
5 P1.0 bidirectional Standard I/O port pin, also ADC channel 0 input, PWM1 capture/pulse positive output PWM1P and serial 2 receive RxD2.
6 P1.1 bidirectional Standard I/O port pin, also ADC channel 1 input, PWM1 pulse negative output PWM1N and serial 2 transmit TxD2.
7 P4.7 bidirectional Standard I/O port pin, also serial 2 TxD2_2, CAN2_TX_3 and LIN_TX_3 outputs.
8 P1.4 bidirectional Standard I/O port pin, also ADC channel 4 input, PWM3 positive output PWM3P, SPI MISO/USART1-SPI/USART2-SPI data input and I2C data line SDA.
9 P1.5 bidirectional Standard I/O port pin, also ADC channel 5 input, PWM3 negative output PWM3N, SPI clock SCLK (plus USART1/USART2 SPI clocks) and I2C clock line SCL.
10 P1.6 bidirectional Standard I/O port pin, also ADC channel 6 input, serial 1 receive RxD_3, PWM4 positive output PWM4P, master clock output MCLKO_2 and external crystal output XTALO.
11 P1.7 bidirectional Standard I/O port pin, also ADC channel 7 input, serial 1 transmit TxD_3, PWM4 negative output PWM4N, PWM5 I/O and external crystal/clock input XTALI.
12 P1.3 bidirectional Standard I/O port pin, also ADC channel 3 input, SPI MOSI (plus USART1/USART2 SPI MOSI), PWM2 negative output PWM2N and Timer 2 clock-divided output T2CLKO.
13 UCAP passive USB core power regulator stabilization pin, connected to an external capacitor (figure shows 0.1 uF to 10 uF).
14 P5.4 bidirectional Standard I/O port pin that can be configured as the active-low reset input nRST (factory default is I/O; reset function requires ISP setting and power cycle), also MCLKO, ADC channel 2, PWM2P, PWM6_2, Timer 2 input T2 and SPI slave select lines.
15 Vcc power_in MCU supply pin (Vcc/AVcc); operating voltage 1.9 V to 5.5 V per the datasheet feature list.
16 ADC_VRef+ input ADC external reference voltage pin, which must be connected to an external reference between 2.4 V and MCU-VCC, since floating it causes leakage current.
17 Gnd power_in Ground pin (Gnd/AGnd), common ground for the digital core and ADC.
18 P4.0 bidirectional Standard I/O port pin, also SPI MOSI_3 and USART1/USART2 SPI MOSI_3 outputs (S1MOSI_3, S2MOSI_3).
19 P3.0 bidirectional Standard I/O port pin with weak pull-up/quasi-bidirectional mode after power-on, also serial 1 receive RxD, USB data line D- and external interrupt INT4; used for USB/serial ISP download.
20 P3.1 bidirectional Standard I/O port pin with weak pull-up/quasi-bidirectional mode after power-on, also serial 1 transmit TxD and USB data line D+; used for USB/serial ISP download and simulation.
21 P3.2 bidirectional Standard I/O port pin, also external interrupt INT0, SPI/I2C pins SCLK_4/SCL_4 and PWM external trigger inputs PWMETI/PWMETI2; held high at power-on and used as the USB-download select pin when low.
22 P3.3 bidirectional Standard I/O port pin, also external interrupt INT1, SPI MISO_4, I2C data SDA_4, PWM4 negative output PWM4N_4 and PWM7 I/O PWM7_2.
23 P3.4 bidirectional Standard I/O port pin, also Timer 0 external clock input T0, Timer 1 clock-divided output T1CLKO, SPI MOSI_4, PWM4 positive output PWM4P_4, PWM8_2 and comparator output CMPO.
24 P5.0 bidirectional Standard I/O port pin, also serial 3 receive RxD3_2, comparator positive input CMP+_2 and CAN receive CAN_RX_2.
25 P5.1 bidirectional Standard I/O port pin, also serial 3 transmit TxD3_2, comparator positive input CMP+_3 and CAN transmit CAN_TX_2.
26 P3.5 bidirectional Standard I/O port pin, also Timer 1 external clock input T1, Timer 0 clock-divided output T0CLKO, SPI slave select SS_4 and enhanced PWM fault input PWMFLT.
27 P3.6 bidirectional Standard I/O port pin, also external interrupt INT2, serial 1 receive RxD_2 and comparator negative input CMP-.
28 P3.7 bidirectional Standard I/O port pin, also external interrupt INT3, serial 1 transmit TxD_2 and comparator positive input CMP+.
29 P4.1 bidirectional Standard I/O port pin, also SPI MISO_3 (plus USART1/USART2 SPI MISO_3 data), comparator output CMPO_2 and PWM external trigger input PWMETI_2.
30 P4.2 bidirectional Standard I/O port pin, also external bus write strobe WR and CAN receive CAN_RX_3.
31 P4.3 bidirectional Standard I/O port pin, also serial 4 receive RxD_4 and SPI clock SCLK_3 (plus USART1/USART2 SPI clocks S1SCLK_3, S2SCLK_3).
32 P4.4 bidirectional Standard I/O port pin, also external bus read strobe RD and serial 4 transmit TxD_4.
33 P2.0 bidirectional Standard I/O port pin, also address bus A8, PWM1 positive output PWM1P_2 and PWM5 I/O.
34 P2.1 bidirectional Standard I/O port pin, also address bus A9, PWM1 negative output PWM1N_2 and PWM6 I/O.
35 P2.2 bidirectional Standard I/O port pin, also address bus A10, PWM2 positive output PWM2P_2, PWM7 I/O and SPI slave select SS_2.
36 P2.3 bidirectional Standard I/O port pin, also address bus A11, PWM2 negative output PWM2N_2, PWM8 I/O and SPI MOSI_2.
37 P2.4 bidirectional Standard I/O port pin, also address bus A12, PWM3 positive output PWM3P_2, I2C data SDA_2 and SPI MISO_2.
38 P2.5 bidirectional Standard I/O port pin, also address bus A13, PWM3 negative output PWM3N_2, I2C clock SCL_2 and SPI clock SCLK_2.
39 P2.6 bidirectional Standard I/O port pin, also address bus A14 and PWM4 positive output PWM4P_2.
40 P2.7 bidirectional Standard I/O port pin, also address bus A15 and PWM4 negative output PWM4N_2.
41 P4.5 bidirectional Standard I/O port pin, also ALE address latch enable output and CAN transmit CAN_TX_3.
42 P4.6 bidirectional Standard I/O port pin, also LIN receive LIN_RX_3, CAN2 receive CAN2_RX_3 and serial 2 receive RxD2_2.
43 P0.0 bidirectional Standard I/O port pin, also address/data bus AD0, ADC channel 8 input, serial 3 receive RxD3, PWM5 I/O PWM5_3, Timer 3 external clock T3_2 and CAN receive CAN_RX.
44 P0.1 bidirectional Standard I/O port pin, also address/data bus AD1, ADC channel 9 input, serial 3 transmit TxD3, PWM6 I/O PWM6_3, Timer 3 clock output T3CLKO_2 and CAN transmit CAN_TX.
45 P0.2 bidirectional Standard I/O port pin, also address/data bus AD2, ADC channel 10 input, serial 4 receive RxD4, PWM7 I/O PWM7_3, Timer 4 external clock T4_2, CAN2 receive CAN2_RX and LIN receive LIN_RX.
46 P0.3 bidirectional Standard I/O port pin, also address/data bus AD3, ADC channel 11 input, serial 4 transmit TxD4, PWM8 I/O PWM8_3, Timer 4 clock output T4CLKO_2, CAN2 transmit CAN2_TX and LIN transmit LIN_TX.
47 P0.4 bidirectional Standard I/O port pin, also address/data bus AD4, ADC channel 12 input and Timer 3 external clock input T3.
48 P5.2 bidirectional Standard I/O port pin, also serial 4 receive RxD4_2, CAN2 receive CAN2_RX_2 and LIN receive LIN_RX_2.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STC Micro
Package QFN-48(6x6)
Category Embedded Processors & Controllers
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIH1 input high level (general I/O), Schmitt trigger on VIH1 1.6 V VSS=0V, VDD=5.0V, 25℃; 打开施密特触发 1657
VIH1 input high level (general I/O), Schmitt trigger off VIH1 1.54 V VSS=0V, VDD=5.0V, 25℃; 关闭施密特触发 1657
VIL1 input low level, Schmitt trigger on VIL1 1.32 V VSS=0V, VDD=5.0V, 25℃; 打开施密特触发 1657
VIL1 input low level, Schmitt trigger off VIL1 1.48 V VSS=0V, VDD=5.0V, 25℃; 关闭施密特触发 1657
Logic 0 input current IIL 50 uA VSS=0V, VDD=5.0V, 25℃; 端口电压 0V 1657
Logic 1 to 0 transition current ITL 100 270 600 uA VSS=0V, VDD=5.0V, 25℃; 端口电压 2.0V 1657
I/O pull-up resistance RPU 4.1 4.2 4.4 KΩ VSS=0V, VDD=5.0V, 25℃ 1657
Internal IRC temperature drift, -20℃~65℃ -0.88 1.05 % 参考温度 25℃, 温度范围 -20℃~65℃ 1656
Internal IRC temperature drift, -40℃~85℃ -1.38 1.42 % 参考温度 25℃, 温度范围 -40℃~85℃ 1656
Internal IRC temperature drift, -40℃~125℃ -3 3 % 参考温度 25℃, 温度范围 -40℃~125℃ 1656
Operating voltage 1.9 5.5 V 当工作温度低于-40℃时，工作电压不得低于 3.0V 1656
VDD to ground voltage -0.3 5.5 V 1656
I/O to ground voltage -0.3 V 1656
Storage temperature -55 155 ℃ 1656
Operating temperature (internal high-speed IRC and external crystal) -40 85 ℃ 使用内部高速 IRC 和外部晶振 1656
Operating temperature (second listed range) -40 125 ℃ 1656

CAD (KiCad official)

  • Symbol: STC32G12K128-35I-QFN48
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • 3D model: QFN-48(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: stc32g12k128-35i-qfn48-etched.step / stc32g12k128-35i-qfn48-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stc32g12k128-35i-qfn48.step / stc32g12k128-35i-qfn48.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STC Micro datasheet (1887 pp, sha256 59bba1d366cc8d33, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF