# STC32G12K128-35I-LQFP64

**STC Micro** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

STC32G12K128-35I-LQFP64 from STC Micro, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P5.3 | bidirectional | Standard bidirectional I/O port P5.3 with alternate functions TxD4_2 (UART4 transmit), CAN2_TX_2 (CAN2 transmit) and LIN_TX_2 (LIN transmit). |
| 2 | P0.5 | bidirectional | Standard I/O port P0.5 with AD5 address/data bus, ADC13 analog input channel 13 and T3CLKO timer 3 clock-divided output. |
| 3 | P0.6 | bidirectional | Standard I/O port P0.6 with AD6 address/data bus, ADC14 analog input channel 14, T4 external clock input for timer 4 and PWMFLT2_2 enhanced PWM external fault-detect input. |
| 4 | P0.7 | bidirectional | Standard I/O port P0.7 with AD7 address/data bus and T4CLKO timer 4 clock-divided output. |
| 5 | P6.0 | bidirectional | Standard I/O port P6.0 with PWM1P_3 PWM1 capture input and positive pulse output. |
| 6 | P6.1 | bidirectional | Standard I/O port P6.1 with PWM1N_3 PWM1 negative pulse output. |
| 7 | P6.2 | bidirectional | Standard I/O port P6.2 with PWM2P_3 PWM2 capture input and positive pulse output. |
| 8 | P6.3 | bidirectional | Standard I/O port P6.3 with PWM2N_3 PWM2 negative pulse output. |
| 9 | P1.0 | bidirectional | Standard I/O port P1.0 with ADC0 analog input channel 0, PWM1P PWM1 positive capture/pulse output and RxD2 UART2 receive. |
| 10 | P1.1 | bidirectional | Standard I/O port P1.1 with ADC1 analog input channel 1, PWM1N PWM1 negative pulse output and TxD2 UART2 transmit. |
| 11 | P4.7 | bidirectional | Standard I/O port P4.7 with TxD2_2 UART2 transmit, CAN2_TX_3 CAN2 transmit and LIN_TX_3 LIN transmit. |
| 12 | P1.4 | bidirectional | Standard I/O port P1.4 with ADC4 analog input channel 4, PWM3P, SPI MISO (and USART1/USART2 SPI MISO), and I2C data line SDA. |
| 13 | P1.5 | bidirectional | Standard I/O port P1.5 with ADC5 analog input channel 5, PWM3N negative pulse output, SPI clock SCLK (and USART1/USART2 SPI clocks) and I2C clock line SCL. |
| 14 | P1.6 | bidirectional | Standard I/O port P1.6 with ADC6 analog input channel 6, RxD_3 UART1 receive, PWM4P, MCLKO_2 main clock divided output and XTALO external crystal output. |
| 15 | P1.7 | bidirectional | Standard I/O port P1.7 with ADC7 analog input channel 7, TxD_3 UART1 transmit, PWM4N, PWM5_2 and XTALI external crystal/external clock input. |
| 16 | P1.3 | bidirectional | Standard I/O port P1.3 with ADC3 analog input channel 3, SPI MOSI (and USART1/USART2 SPI MOSI), PWM2N negative pulse output and T2CLKO timer 2 clock-divided output. |
| 17 | UCAP | passive | USB core supply regulator pin (UCAP) that is connected to an external decoupling capacitor. |
| 18 | P5.4 | bidirectional | Standard I/O port P5.4 that can be configured by ISP as the active-low reset pin nRST, with alternate functions including MCLKO, SPI/USART slave selects, PWM2P, PWM6_2, T2 and ADC2. |
| 19 | Vcc | power_in | Power supply pin Vcc, which also supplies the ADC as AVcc. |
| 20 | Vref+ | power_in | ADC reference voltage pin ADC_VRef+ that must be connected to an external reference voltage between 2.4V and MCU-VCC, since floating it causes leakage current. |
| 21 | Gnd | power_in | Ground pin Gnd, shared with AGnd (ADC ground) and Vref- (ADC reference ground). |
| 22 | P4.0 | bidirectional | Standard I/O port P4.0 with SPI MOSI_3 master output/slave input (and USART1/USART2 SPI MOSI). |
| 23 | P6.4 | bidirectional | Standard I/O port P6.4 with PWM3P_3 PWM3 capture/positive pulse output and S1SS_4 USART1 SPI slave select. |
| 24 | P6.5 | bidirectional | Standard I/O port P6.5 with PWM3N_3 PWM3 negative pulse output and S1MOSI_4 USART1 SPI MOSI. |
| 25 | P6.6 | bidirectional | Standard I/O port P6.6 with PWM4P_3 PWM4 capture/positive pulse output and S1MISO_4 USART1 SPI MISO. |
| 26 | P6.7 | bidirectional | Standard I/O port P6.7 with PWM4N_3 PWM4 negative pulse output and S1SCLK_4 USART1 SPI clock. |
| 27 | P3.0 | bidirectional | Port P3.0 that is also the USB D- data line, UART1 RxD receive and external interrupt INT4; it is quasi-bidirectional (weak pull-up) after power-on. |
| 28 | P3.1 | bidirectional | Port P3.1 that is also the USB D+ data line and UART1 TxD transmit; it is quasi-bidirectional (weak pull-up) after power-on. |
| 29 | P3.2 | bidirectional | Standard I/O port P3.2 with external interrupt INT0, SPI clock SCLK_4, I2C clock SCL_4 and PWM external trigger inputs PWMETI and PWMETI2. |
| 30 | P3.3 | bidirectional | Standard I/O port P3.3 with external interrupt INT1, SPI MISO_4, I2C data SDA_4, PWM4N_4 negative pulse output and PWM7_2. |
| 31 | P3.4 | bidirectional | Standard I/O port P3.4 with timer 0 external clock input T0, T1CLKO timer 1 clock output, SPI MOSI_4, PWM4P_4, PWM8_2 and comparator output CMPO. |
| 32 | P5.0 | bidirectional | Standard I/O port P5.0 with UART3 receive RxD3_2, comparator positive input CMP+_2 and CAN receive CAN_RX_2. |
| 33 | P5.1 | bidirectional | Standard I/O port P5.1 with UART3 transmit TxD3_2, comparator positive input CMP+_3 and CAN transmit CAN_TX_2. |
| 34 | P3.5 | bidirectional | Standard I/O port P3.5 with timer 1 external clock input T1, T0CLKO timer 0 clock output, SPI slave select SS_4 and enhanced PWM external fault input PWMFLT. |
| 35 | P3.6 | bidirectional | Standard I/O port P3.6 with external interrupt INT2, UART1 receive RxD_2 and comparator negative input CMP-. |
| 36 | P3.7 | bidirectional | Standard I/O port P3.7 with external interrupt INT3, UART1 transmit TxD_2 and comparator positive input CMP+. |
| 37 | P7.0 | bidirectional | Standard I/O port P7.0 with CAN_RX_4 CAN receive function. |
| 38 | P7.1 | bidirectional | Standard I/O port P7.1 with CAN_TX_4 CAN transmit function. |
| 39 | P7.2 | bidirectional | Standard I/O port P7.2 with CAN2_RX_4 CAN2 receive and LIN_RX_4 LIN receive functions. |
| 40 | P7.3 | bidirectional | Standard I/O port P7.3 with CAN2_TX_4 and LIN_TX_4 transmit functions and PWMETI_3 PWM external trigger input. |
| 41 | P4.1 | bidirectional | Standard I/O port P4.1 with SPI MISO_3 (and USART1/USART2 SPI MISO), comparator output CMPO_2 and PWMETI_2 PWM external trigger input. |
| 42 | P4.2 | bidirectional | Standard I/O port P4.2 with WR (external bus write strobe) and CAN_RX_3 CAN receive. |
| 43 | P4.3 | bidirectional | Standard I/O port P4.3 with UART4 receive RxD_4, SPI clocks SCLK_3, S1SCLK_3 and S2SCLK_3. |
| 44 | P4.4 | bidirectional | Standard I/O port P4.4 with RD (external bus read strobe) and TxD_4 UART4 transmit. |
| 45 | P2.0 | bidirectional | Standard I/O port P2.0 with address bus A8, PWM1P_2 positive pulse output and PWM5 channel. |
| 46 | P2.1 | bidirectional | Standard I/O port P2.1 with address bus A9, PWM1N_2 negative pulse output and PWM6 channel. |
| 47 | P2.2 | bidirectional | Standard I/O port P2.2 with address bus A10, PWM2P_2, PWM7, SPI slave select SS_2 and USART1/USART2 SPI slave selects S1SS_2 and S2SS_2. |
| 48 | P2.3 | bidirectional | Standard I/O port P2.3 with address bus A11, PWM2N_2, PWM8, SPI MOSI_2 and USART1/USART2 SPI MOSI S1MOSI_2 and S2MOSI_2. |
| 49 | P2.4 | bidirectional | Standard I/O port P2.4 with address bus A12, PWM3P_2, I2C data SDA_2, SPI MISO_2 and USART1/USART2 SPI MISO S1MISO_2 and S2MISO_2. |
| 50 | P2.5 | bidirectional | Standard I/O port P2.5 with address bus A13, PWM3N_2, I2C clock SCL_2, SPI clock SCLK_2 and USART1/USART2 SPI clocks S1SCLK_2 and S2SCLK_2. |
| 51 | P2.6 | bidirectional | Standard I/O port P2.6 with address bus A14 and PWM4P_2 positive pulse output. |
| 52 | P2.7 | bidirectional | Standard I/O port P2.7 with address bus A15 and PWM4N_2 negative pulse output. |
| 53 | P7.4 | bidirectional | Standard I/O port P7.4 with USART2 SPI slave select S2SS_4 and PWM5_4. |
| 54 | P7.5 | bidirectional | Standard I/O port P7.5 with USART2 SPI MOSI S2MOSI_4 and PWM6_4. |
| 55 | P7.6 | bidirectional | Standard I/O port P7.6 with USART2 SPI MISO S2MISO_4 and PWM7_4. |
| 56 | P7.7 | bidirectional | Standard I/O port P7.7 with USART2 SPI clock S2SCLK_4 and PWM8_4. |
| 57 | P4.5 | bidirectional | Standard I/O port P4.5 with ALE (external address latch enable) and CAN_TX_3 CAN transmit. |
| 58 | P4.6 | bidirectional | Standard I/O port P4.6 with LIN_RX_3 LIN receive, CAN2_RX_3 CAN2 receive and RxD2_2 UART2 receive. |
| 59 | P0.0 | bidirectional | Standard I/O port P0.0 with AD0 address/data bus, ADC8 analog input channel 8, RxD3 UART3 receive, PWM5_3, T3_2 timer 3 external clock input and CAN_RX CAN receive. |
| 60 | P0.1 | bidirectional | Standard I/O port P0.1 with AD1 address/data bus, ADC9 analog input channel 9, TxD3 UART3 transmit, PWM6_3, T3CLKO_2 timer 3 clock output and CAN_TX CAN transmit. |
| 61 | P0.2 | bidirectional | Standard I/O port P0.2 with AD2 address/data bus, ADC10 analog input channel 10, RxD4 UART4 receive, PWM7_3, T4_2 timer 4 external clock input, CAN2_RX and LIN_RX. |
| 62 | P0.3 | bidirectional | Standard I/O port P0.3 with AD3 address/data bus, ADC11 analog input channel 11, TxD4 UART4 transmit, PWM8_3, T4CLKO_2 timer 4 clock output, CAN2_TX and LIN_TX. |
| 63 | P0.4 | bidirectional | Standard I/O port P0.4 with AD4 address/data bus, ADC12 analog input channel 12 and T3 timer 3 external clock input. |
| 64 | P5.2 | bidirectional | Standard I/O port P5.2 with UART4 receive RxD4_2, CAN2 receive CAN2_RX_2 and LIN receive LIN_RX_2. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STC Micro |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 存储温度 |  | -55 |  | 155 | ℃ |  | 1656 |
| 工作温度 |  | -40 |  | 85 | ℃ | 使用内部高速 IRC 和外部晶振 | 1656 |
| 工作温度 |  | -40 |  | 125 | ℃ |  | 1656 |
| 工作电压 |  | 1.9 |  | 5.5 | V | 当工作温度低于-40℃时，工作电压不得低于 3.0V | 1656 |
| VDD 对地电压 | VDD | -0.3 |  | 5.5 | V |  | 1656 |
| I/O 口对地电压 |  | -0.3 |  |  | V | 最大值为 VDD+0.3 V（表中以表达式给出，数值无法填写） | 1656 |
| 内部 IRC 温漂特性（-20℃~65℃） |  | -0.88 |  | 1.05 | % | 参考温度 25℃ | 1656 |
| 内部 IRC 温漂特性（-40℃~85℃） |  | -1.38 |  | 1.42 | % | 参考温度 25℃ | 1656 |
| 内部 IRC 温漂特性（-40℃~125℃） |  | -3 |  | 3 | % | 参考温度 25℃ | 1656 |
| 低压复位门槛电压 POR | POR |  | 1.9 |  | V | 测试温度 25℃ | 1656 |
| 低压复位门槛电压 LVR0 | LVR0 |  | 2 |  | V | 测试温度 25℃ | 1656 |
| 低压复位门槛电压 LVR1 | LVR1 |  | 2.4 |  | V | 测试温度 25℃ | 1656 |
| 低压复位门槛电压 LVR2 | LVR2 |  | 2.7 |  | V | 测试温度 25℃ | 1656 |
| 低压复位门槛电压 LVR3 | LVR3 |  | 3 |  | V | 测试温度 25℃ | 1656 |
| 输入低电平（普通 I/O） | VIL1 |  |  | 1.32 | V | 打开施密特触发 | 1657 |
| 输入低电平（普通 I/O） | VIL1 |  |  | 1.48 | V | 关闭施密特触发 | 1657 |
| 输入高电平（普通 I/O） | VIH1 | 1.6 |  |  | V | 打开施密特触发 | 1657 |
| 输入高电平（普通 I/O） | VIH1 | 1.54 |  |  | V | 关闭施密特触发 | 1657 |
| 逻辑 0 输入电流 | IIL |  |  | 50 | uA | 端口电压 0V | 1657 |
| 逻辑 1 到 0 的转移电流 | ITL | 100 | 270 | 600 | uA | 端口电压 2.0V | 1657 |
| I/O 口上拉电阻 | RPU | 4.1 | 4.2 | 4.4 | KΩ |  | 1657 |
| 普通工作模式电流 | ICC | 4 |  | 20 | mA |  | 1657 |
| 掉电模式电流 | IPD |  | 1 |  | uA |  | 1657 |
| 掉电唤醒定时器 | IWKT |  | 4.1 |  | uA |  | 1657 |
| 低压检测模块 | ILVD |  | 425 |  | uA |  | 1657 |
| 空闲模式电流（6MHz） | IIDL |  | 1.55 |  | mA |  | 1657 |
| 空闲模式电流（11.0592MHz） | IIDL |  | 2.34 |  | mA |  | 1657 |
| 空闲模式电流（24MHz） | IIDL |  | 3.93 |  | mA |  | 1657 |
| 空闲模式电流（内部 32KHz） | IIDL |  | 0.57 |  | mA |  | 1657 |
| 正常模式电流（6MHz） | INOR |  | 2.2 |  | mA |  | 1657 |
| 正常模式电流（11.0592MHz） | INOR |  | 3.61 |  | mA |  | 1657 |
| 正常模式电流（24MHz） | INOR |  | 6.45 |  | mA |  | 1657 |
| 正常模式电流（内部 32KHz） | INOR |  | 0.57 |  | mA |  | 1657 |
| 输出低电平的灌电流 | IOL1 |  | 20 |  | mA | 端口电压 0.45V | 1657 |
| 输出高电平电流（双向模式） | IOH1 |  | 200 |  | uA |  | 1657 |
| 输出高电平电流（推挽模式） | IOH2 |  | 20 |  | mA | 端口电压 2.4V | 1657 |
| 使能比较器时掉电模式功耗 | IPD2 |  | 460 |  | uA |  | 1657 |
| 使能 LVD 时掉电模式功耗 | IPD3 |  | 520 |  | uA |  | 1657 |

## CAD (KiCad official)

- Symbol: `STC32G12K128-35I-LQFP64`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `stc32g12k128-35i-lqfp64-etched.step` / `stc32g12k128-35i-lqfp64-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stc32g12k128-35i-lqfp64.step` / `stc32g12k128-35i-lqfp64.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STC Micro datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8756362524260884480) (1887 pp, sha256 `59bba1d366cc8d33`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stc32g12k128-35i-lqfp64-datasheet.pdf)