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STC15W4K56S4-30I-LQFP44

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STC Micro Microcontrollers (MCU/MPU/SOC), LQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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STC15W4K56S4-30I-LQFP44

STC Micro · Microcontrollers (MCU/MPU/SOC) · LQFP-44(10x10)

STC15W4K56S4-30I-LQFP44 from STC Micro, in a LQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P0.5 bidirectional Port 0 bit 5 standard I/O (PORT0[5]) that also serves as address/data bus AD5, Timer 3 external input T3, and PWM fault-stop input PWMFLT_2 when PWM2345_S is set.
2 P0.6 bidirectional Port 0 bit 6 I/O that also serves as AD6, Timer 4 clock output T4CLKO, and PWM7_2 output channel 7; it is high-impedance input after power-on and must be set to another mode before use, and needs an external pull-up if it is high-impedance in power-down mode.
3 P0.7 bidirectional Port 0 bit 7 I/O that also serves as AD7, Timer 4 external input T4, and PWM6_2 output channel 6; it is high-impedance input after power-on and must be set to another mode before use, and needs an external pull-up if it is high-impedance in power-down mode.
4 P1.0 bidirectional Port 1 bit 0 standard I/O (PORT1[0]) that also serves as ADC input channel 0, CCP1 capture/PWM output, and UART2 receive RxD2.
5 P1.1 bidirectional Port 1 bit 1 standard I/O (PORT1[1]) that also serves as ADC input channel 1, CCP0 capture/PWM output, and UART2 transmit TxD2.
6 P4.7/TxD2_2 bidirectional Port 4 bit 7 standard I/O (PORT4[7]) that serves as the alternate UART2 transmit pin TxD2_2.
7 P1.2 bidirectional Port 1 bit 2 standard I/O (PORT1[2]) that also serves as ADC input channel 2, SPI slave select SS, CCP/PCA external pulse input ECI, and comparator output CMPO.
8 P1.3 bidirectional Port 1 bit 3 standard I/O (PORT1[3]) that also serves as ADC input channel 3 and SPI master-out/slave-in MOSI.
9 P1.4 bidirectional Port 1 bit 4 standard I/O (PORT1[4]) that also serves as ADC input channel 4 and SPI master-in/slave-out MISO.
10 P1.5 bidirectional Port 1 bit 5 standard I/O (PORT1[5]) that also serves as ADC input channel 5 and the SPI serial clock SCLK.
11 P1.6 bidirectional Port 1 bit 6 I/O that also serves as ADC input channel 6, UART1 alternate receive RxD_3, XTAL2 crystal amplifier output, system clock output SysClkO_2, and PWM6 output; it is high-impedance input after power-on and must be set to another mode before use.
12 P1.7 bidirectional Port 1 bit 7 I/O that also serves as ADC input channel 7, UART1 alternate transmit TxD_3, XTAL1 crystal amplifier input (external clock input when no crystal is used), and PWM7 output; it is high-impedance input after power-on and must be set to another mode before use.
13 P5.4/RST/SysClkO/SS_3/CMP- bidirectional Port 5 bit 4 standard I/O (PORT5[4]) that also serves as active-high reset input RST, system clock output SysClkO, SPI slave select SS_3, and comparator negative input CMP-, which must be set high-impedance when used as a comparator input.
14 Vcc power_in Positive power supply; the series operates from 2.5 V to 5.5 V.
15 P5.5/CMP+ bidirectional Port 5 bit 5 standard I/O (PORT5[5]) that also serves as comparator positive input CMP+, which must be set high-impedance when used as a comparator input.
16 Gnd power_in Power supply ground.
17 P4.0/MOSI_3 bidirectional Port 4 bit 0 standard I/O (PORT4[0]) that also serves as the alternate SPI master-out/slave-in pin MOSI_3.
18 P3.0/RxD/INT4/T2CLKO bidirectional Port 3 bit 0 standard I/O (PORT3[0]) that also serves as UART1 receive RxD, external interrupt INT4 (falling edge only, wake-up capable), and Timer 2 clock output T2CLKO.
19 P3.1/TxD/T2 bidirectional Port 3 bit 1 standard I/O (PORT3[1]) that also serves as UART1 transmit TxD and Timer 2 external counter input T2.
20 P3.2/INT0 bidirectional Port 3 bit 2 standard I/O (PORT3[2]) that also serves as external interrupt INT0, which is falling-edge only if IT0 is set and rising/falling-edge if IT0 is cleared, and supports power-down wake-up.
21 P3.3/INT1 bidirectional Port 3 bit 3 standard I/O (PORT3[3]) that also serves as external interrupt INT1, which is falling-edge only if IT1 is set and rising/falling-edge if IT1 is cleared, and supports power-down wake-up.
22 P3.4/T0/T1CLKO/ECI_2 bidirectional Port 3 bit 4 standard I/O (PORT3[4]) that also serves as Timer 0 external input T0, Timer 1 clock output T1CLKO, and CCP/PCA external pulse input ECI_2.
23 P3.5/T1/T0CLKO/CCP0_2 bidirectional Port 3 bit 5 standard I/O (PORT3[5]) that also serves as Timer 1 external input T1, Timer 0 clock output T0CLKO, and CCP0 alternate channel CCP0_2.
24 P3.6/INT2/RxD_2/CCP1_2 bidirectional Port 3 bit 6 standard I/O (PORT3[6]) that also serves as falling-edge-only external interrupt INT2 with power-down wake-up, UART1 alternate receive RxD_2, and CCP1 alternate channel CCP1_2.
25 P3.7/INT3/TxD_2/PWM2 bidirectional Port 3 bit 7 standard I/O (PORT3[7]) that also serves as falling-edge-only external interrupt INT3 with power-down wake-up, UART1 alternate transmit TxD_2, and PWM2 output; it is high-impedance input after power-on and must be set to another mode before use.
26 P4.1/MISO_3 bidirectional Port 4 bit 1 standard I/O (PORT4[1]) that also serves as the alternate SPI master-in/slave-out pin MISO_3.
27 P4.2/WR/PWM5_2 bidirectional Port 4 bit 2 standard I/O (PORT4[2]) that also serves as external data memory write strobe WR and PWM5_2 output channel 5; it is high-impedance input after power-on and must be set to another mode before use.
28 P4.3/SCLK_3 bidirectional Port 4 bit 3 standard I/O (PORT4[3]) that also serves as the alternate SPI serial clock SCLK_3.
29 P4.4/RD/PWM4_2 bidirectional Port 4 bit 4 standard I/O (PORT4[4]) that also serves as external data memory read strobe RD and PWM4_2 output channel 4; it is high-impedance input after power-on and must be set to another mode before use.
30 P2.0 bidirectional Port 2 bit 0 standard I/O (PORT2[0]) that also serves as address bus bit A8 and RSTOUT_LOW, which is driven low after power-on and during reset and can be set high or low by software.
31 P2.1/A9/SCLK_2/PWM3 bidirectional Port 2 bit 1 standard I/O (PORT2[1]) that also serves as address bus bit A9, alternate SPI clock SCLK_2, and PWM3 output channel 3; it is high-impedance input after power-on and must be set to another mode before use.
32 P2.2/A10/MISO_2/PWM4 bidirectional Port 2 bit 2 standard I/O (PORT2[2]) that also serves as address bus bit A10, alternate SPI master-in/slave-out MISO_2, and PWM4 output channel 4; it is high-impedance input after power-on and must be set to another mode before use.
33 P2.3/A11/MOSI_2/PWM5 bidirectional Port 2 bit 3 standard I/O (PORT2[3]) that also serves as address bus bit A11, alternate SPI master-out/slave-in MOSI_2, and PWM5 output channel 5; it is high-impedance input after power-on and must be set to another mode before use.
34 P2.4/A12/ECI_3/SS_2/PWMFLT bidirectional Port 2 bit 4 standard I/O (PORT2[4]) that also serves as address bus bit A12, CCP/PCA external pulse input ECI_3, alternate SPI slave select SS_2, and PWM fault-stop input PWMFLT.
35 P2.5/A13/CCP0_3 bidirectional Port 2 bit 5 standard I/O (PORT2[5]) that also serves as address bus bit A13 and CCP0 alternate channel CCP0_3 for capture, high-speed output, or PWM.
36 P2.6/A14/CCP1_3 bidirectional Port 2 bit 6 standard I/O (PORT2[6]) that also serves as address bus bit A14 and CCP1 alternate channel CCP1_3 for capture, high-speed output, or PWM.
37 P2.7 bidirectional Port 2 bit 7 standard I/O (PORT2[7]) that also serves as address bus bit A15 and PWM2_2 output channel 2; it is high-impedance input after power-on and must be set to another mode before use.
38 P4.5 bidirectional Port 4 bit 5 standard I/O (PORT4[5]) that also serves as address latch enable ALE and PWM3_2 output channel 3; it is high-impedance input after power-on and must be set to another mode before use.
39 P4.6/RxD2_2 bidirectional Port 4 bit 6 standard I/O (PORT4[6]) that serves as the alternate UART2 receive pin RxD2_2.
40 P0.0 bidirectional Port 0 bit 0 standard I/O (PORT0[0]) that also serves as address/data bus AD0 and UART3 receive RxD3.
41 P0.1 bidirectional Port 0 bit 1 standard I/O (PORT0[1]) that also serves as address/data bus AD1 and UART3 transmit TxD3.
42 P0.2 bidirectional Port 0 bit 2 standard I/O (PORT0[2]) that also serves as address/data bus AD2 and UART4 receive RxD4.
43 P0.3 bidirectional Port 0 bit 3 standard I/O (PORT0[3]) that also serves as address/data bus AD3 and UART4 transmit TxD4.
44 P0.4 bidirectional Port 0 bit 4 standard I/O (PORT0[4]) that also serves as address/data bus AD4 and Timer 3 clock output T3CLKO.

Key specifications

Parameter Value
Manufacturer STC Micro
Package LQFP-44(10x10)
Category Embedded Processors & Controllers
Pins 44

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Current ICC 4 20 mA 5V 1184
Input Low (P0,P1,P2,P3) VIL1 0.8 V 5V 1184
Input High (P0,P1,P2,P3) VIH1 2 V 5V 1184
Input High (RESET) VIH2 2.2 V 5V 1184
Sourcing Current for output high (P0,P1,P2,P3)(Quasi-output) IOH1 200 270 uA 5V 1184
Logic 0 input current (P0,P1,P2,P3) IIL 50 uA Vpin=0V 1184
Logic 1 to 0 transition current (P0,P1,P2,P3) ITL 100 270 600 uA Vpin=2.0V 1184
Operating Current ICC 4 10 mA 3.3V 1184
Sourcing Current for output high (P0,P1,P2,P3)(Quasi-output) IOH1 140 170 uA 3.3V 1184
Logic 0 input current (P0,P1,P2,P3) IIL 8 50 uA Vpin=0V 1184
Logic 1 to 0 transition current (P0,P1,P2,P3) ITL 110 600 uA Vpin=2.0V 1184
VDD Operating Voltage (5V MCU) VDD 3.3 5 5.5 V 1184
VDD Operating Voltage (3V MCU) VDD 2.4 3.3 3.6 V 1184
Storage temperature TST -55 125 ℃ 1184
Operating temperature (I) TA -40 85 ℃ 1184
DC power supply (5V) VDD - VSS -0.3 5.5 V 1184
DC power supply (3V) VDD - VSS -0.3 3.6 V 1184
Voltage on any pin (upper limit printed as VCC + 0.3) -0.3 V 1184

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the following 441

CAD (KiCad official)

  • Symbol: STC15W4K56S4-30I-LQFP44
  • Footprint: Package_QFP:LQFP-44_10x10mm_P0.8mm
  • 3D model: LQFP-44(10x10) (KiCad packages3D, STEP)
  • 3D model files: stc15w4k56s4-30i-lqfp44-etched.step / stc15w4k56s4-30i-lqfp44-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stc15w4k56s4-30i-lqfp44.step / stc15w4k56s4-30i-lqfp44.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STC Micro datasheet (1219 pp, sha256 cc8c299c891646e0, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF