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STC15W4K48S4-30I-LQFP44
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STC Micro Microcontrollers (MCU/MPU/SOC), LQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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STC15W4K48S4-30I-LQFP44
STC Micro · Microcontrollers (MCU/MPU/SOC) · LQFP-44(10x10)
STC15W4K48S4-30I-LQFP44 from STC Micro, in a LQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0.5 | bidirectional | Standard I/O port pin P0.5 (PORT0[5]) that also serves as AD5 address/data bus bit, Timer 3 external input T3, and PWMFLT_2 PWM exception-stop input; it is quasi-bidirectional with weak pull-up after reset. |
| 2 | P0.6 | bidirectional | Standard I/O port pin P0.6 (PORT0[6]) that also serves as AD6 address/data bus bit, T4CLKO Timer 4 clock output, and PWM7_2 output channel 7; it is high-impedance input after power-on, so it must be set to another mode before use and needs an external pull-up if high-impedance in power-down mode. |
| 3 | P0.7 | bidirectional | Standard I/O port pin P0.7 (PORT0[7]) that also serves as AD7 address/data bus bit, Timer 4 external input T4, and PWM6_2 output channel 6; it is high-impedance input after power-on, so it must be configured before use and needs an external pull-up if high-impedance in power-down mode. |
| 4 | P1.0 | bidirectional | Standard I/O port pin P1.0 (PORT1[0]) that also serves as ADC0 analog input channel 0, CCP1 capture/PWM channel 1, and RxD2 UART2 receive input. |
| 5 | P1.1 | bidirectional | Standard I/O port pin P1.1 (PORT1[1]) that also serves as ADC1 analog input channel 1, CCP0 capture/PWM channel 0, and TxD2 UART2 transmit output. |
| 6 | P4.7 | bidirectional | Standard I/O port pin P4.7 (PORT4[7]) that also serves as TxD2_2, the alternate UART2 transmit output. |
| 7 | P1.2 | bidirectional | Standard I/O port pin P1.2 (PORT1[2]) that also serves as ADC2 analog input channel 2, SPI slave select SS, CCP/PCA external clock input ECI, and comparator output CMPO. |
| 8 | P1.3 | bidirectional | Standard I/O port pin P1.3 (PORT1[3]) that also serves as ADC3 analog input channel 3 and SPI MOSI (master out / slave in). |
| 9 | P1.4 | bidirectional | Standard I/O port pin P1.4 (PORT1[4]) that also serves as ADC4 analog input channel 4 and SPI MISO (master in / slave out). |
| 10 | P1.5 | bidirectional | Standard I/O port pin P1.5 (PORT1[5]) that also serves as ADC5 analog input channel 5 and SPI SCLK clock signal. |
| 11 | P1.6 | bidirectional | Standard I/O port pin P1.6 (PORT1[6]) that also serves as ADC6 input, RxD_3 UART1 alternate receive, SysClkO_2 system clock output, PWM6 output channel 6 (high-impedance after power-on), and XTAL2 crystal amplifier output. |
| 12 | P1.7 | bidirectional | Standard I/O port pin P1.7 (PORT1[7]) that also serves as ADC7 input, TxD_3 UART1 alternate transmit, PWM7 output channel 7 (high-impedance after power-on), and XTAL1 crystal amplifier input or external clock input. |
| 13 | P5.4 | bidirectional | Standard I/O port pin P5.4 (PORT5[4]) that also serves as RST active-high reset input, SysClkO system clock output, SPI slave select SS_3, and comparator negative input CMP-, which must be set to high-impedance input when used as CMP-. |
| 14 | Vcc | power_in | Positive power supply pin; the STC15W4K32S4 series operates from 2.5 V to 5.5 V. |
| 15 | P5.5 | bidirectional | Standard I/O port pin P5.5 (PORT5[5]) that also serves as comparator positive input CMP+, which must be set to high-impedance input when used as CMP+. |
| 16 | Gnd | power_in | Ground (negative power supply) pin. |
| 17 | P4.0 | bidirectional | Standard I/O port pin P4.0 (PORT4[0]) that also serves as SPI MOSI_3 alternate pin per the pin map (the description table lists it as MISO_3). |
| 18 | P3.0 | bidirectional | Standard I/O port pin P3.0 (PORT3[0]) that also serves as UART1 receive RxD, external interrupt INT4 (falling edge only, power-down wake-up capable), and T2CLKO Timer 2 clock output; P3.0/P3.1 are also used for download and emulation. |
| 19 | P3.1 | bidirectional | Standard I/O port pin P3.1 (PORT3[1]) that also serves as UART1 transmit TxD and external count input T2 for Timer 2. |
| 20 | P3.2 | bidirectional | Standard I/O port pin P3.2 (PORT3[2]) that also serves as external interrupt INT0, which triggers on rising and falling edges (falling edge only when IT0 is set) and supports power-down wake-up. |
| 21 | P3.3 | bidirectional | Standard I/O port pin P3.3 (PORT3[3]) that also serves as external interrupt INT1, which triggers on rising and falling edges (falling edge only when IT1 is set) and supports power-down wake-up. |
| 22 | P3.4 | bidirectional | Standard I/O port pin P3.4 (PORT3[4]) that also serves as Timer 0 external input T0, T1CLKO Timer 1 clock output, and CCP/PCA external clock input ECI_2. |
| 23 | P3.5 | bidirectional | Standard I/O port pin P3.5 (PORT3[5]) that also serves as Timer 1 external input T1, T0CLKO Timer 0 clock output, and CCP0_2 capture/PWM channel 0. |
| 24 | P3.6 | bidirectional | Standard I/O port pin P3.6 (PORT3[6]) that also serves as external interrupt INT2 (falling edge only, power-down wake-up capable), UART1 alternate receive RxD_2, and CCP1_2 capture/PWM channel 1. |
| 25 | P3.7 | bidirectional | Standard I/O port pin P3.7 (PORT3[7]) that also serves as external interrupt INT3 (falling edge only, power-down wake-up capable), UART1 alternate transmit TxD_2, and PWM2 output channel 2 (high-impedance after power-on). |
| 26 | P4.1 | bidirectional | Standard I/O port pin P4.1 (PORT4[1]) that also serves as SPI MISO_3 alternate pin per the pin map (the description table lists it as MOSI_3). |
| 27 | P4.2 | bidirectional | Standard I/O port pin P4.2 (PORT4[2]) that also serves as external data memory write strobe WR and PWM5_2 output channel 5 (high-impedance after power-on). |
| 28 | P4.3 | bidirectional | Standard I/O port pin P4.3 (PORT4[3]) that also serves as SPI SCLK_3 alternate clock signal. |
| 29 | P4.4 | bidirectional | Standard I/O port pin P4.4 (PORT4[4]) that also serves as external data memory read strobe RD and PWM4_2 output channel 4 (high-impedance after power-on). |
| 30 | P2.0 | bidirectional | Standard I/O port pin P2.0 (PORT2[0]) that also serves as address bus bit A8 and RSTOUT_LOW, which outputs low after power-on and during reset. |
| 31 | P2.1 | bidirectional | Standard I/O port pin P2.1 (PORT2[1]) that also serves as address bus bit A9, SPI SCLK_2 alternate clock, and PWM3 output channel 3 (high-impedance after power-on). |
| 32 | P2.2 | bidirectional | Standard I/O port pin P2.2 (PORT2[2]) that also serves as address bus bit A10, SPI MISO_2 alternate pin, and PWM4 output channel 4 (high-impedance after power-on). |
| 33 | P2.3 | bidirectional | Standard I/O port pin P2.3 (PORT2[3]) that also serves as address bus bit A11, SPI MOSI_2 alternate pin, and PWM5 output channel 5 (high-impedance after power-on). |
| 34 | P2.4 | bidirectional | Standard I/O port pin P2.4 (PORT2[4]) that also serves as address bus bit A12, CCP/PCA external clock input ECI_3, SPI slave select SS_2, and PWM exception-stop input PWMFLT. |
| 35 | P2.5 | bidirectional | Standard I/O port pin P2.5 (PORT2[5]) that also serves as address bus bit A13 and CCP0_3 capture/PWM channel 0. |
| 36 | P2.6 | bidirectional | Standard I/O port pin P2.6 (PORT2[6]) that also serves as address bus bit A14 and CCP1_3 capture/PWM channel 1. |
| 37 | P2.7 | bidirectional | Standard I/O port pin P2.7 (PORT2[7]) that also serves as address bus bit A15 and PWM2_2 output channel 2 (high-impedance after power-on). |
| 38 | P4.5 | bidirectional | Standard I/O port pin P4.5 (PORT4[5]) that also serves as address latch enable ALE and PWM3_2 output channel 3 (high-impedance after power-on). |
| 39 | P4.6 | bidirectional | Standard I/O port pin P4.6 (PORT4[6]) that also serves as UART2 alternate receive RxD2_2. |
| 40 | P0.0 | bidirectional | Standard I/O port pin P0.0 (PORT0[0]) that also serves as address/data bus bit AD0 and UART3 receive RxD3; Port 0 is quasi-bidirectional with weak pull-up after reset. |
| 41 | P0.1 | bidirectional | Standard I/O port pin P0.1 (PORT0[1]) that also serves as address/data bus bit AD1 and UART3 transmit TxD3. |
| 42 | P0.2 | bidirectional | Standard I/O port pin P0.2 (PORT0[2]) that also serves as address/data bus bit AD2 and UART4 receive RxD4. |
| 43 | P0.3 | bidirectional | Standard I/O port pin P0.3 (PORT0[3]) that also serves as address/data bus bit AD3 and UART4 transmit TxD4. |
| 44 | P0.4 | bidirectional | Standard I/O port pin P0.4 (PORT0[4]) that also serves as address/data bus bit AD4 and T3CLKO Timer 3 clock output. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STC Micro |
| Package | LQFP-44(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 44 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature | TST | -55 | 125 | ℃ | 1184 | ||
| Operating temperature (I) | TA | -40 | 85 | ℃ | 1184 | ||
| DC power supply (5V) | VDD - VSS | -0.3 | 5.5 | V | 1184 | ||
| DC power supply (3V) | VDD - VSS | -0.3 | 3.6 | V | 1184 | ||
| Voltage on any pin | -0.3 | V | max printed as VCC + 0.3 | 1184 | |||
| Operating Voltage (5V MCU) | VDD | 3.3 | 5 | 5.5 | V | 1184 | |
| Operating Current (5V MCU) | ICC | 4 | 20 | mA | 5V | 1184 | |
| Input Low (P0,P1,P2,P3) (5V MCU) | VIL1 | 0.8 | V | 5V | 1184 | ||
| Input High (P0,P1,P2,P3) (5V MCU) | VIH1 | 2 | V | 5V | 1184 | ||
| Input High (RESET) (5V MCU) | VIH2 | 2.2 | V | 5V | 1184 | ||
| Sourcing Current for output high (P0,P1,P2,P3)(Quasi-output) (5V MCU) | IOH1 | 200 | 270 | uA | 5V | 1184 | |
| Logic 0 input current (P0,P1,P2,P3) (5V MCU) | IIL | 50 | uA | Vpin=0V | 1184 | ||
| Logic 1 to 0 transition current (P0,P1,P2,P3) (5V MCU) | ITL | 100 | 270 | 600 | uA | Vpin=2.0V | 1184 |
| Operating Voltage (3V MCU) | VDD | 2.4 | 3.3 | 3.6 | V | 1184 | |
| Operating Current (3V MCU) | ICC | 4 | 10 | mA | 3.3V | 1184 | |
| Input Low (P0,P1,P2,P3) (3V MCU) | VIL1 | 0.8 | V | 3.3V | 1184 | ||
| Input High (P0,P1,P2,P3) (3V MCU) | VIH1 | 2 | V | 3.3V | 1184 | ||
| Input High (RESET) (3V MCU) | VIH2 | 2.2 | V | 3.3V | 1184 | ||
| Sourcing Current for output high (P0,P1,P2,P3)(Quasi-output) (3V MCU) | IOH1 | 140 | 170 | uA | 3.3V | 1184 | |
| Logic 0 input current (P0,P1,P2,P3) (3V MCU) | IIL | 8 | 50 | uA | Vpin=0V | 1184 | |
| Logic 1 to 0 transition current (P0,P1,P2,P3) (3V MCU) | ITL | 110 | 600 | uA | Vpin=2.0V | 1184 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the following | 441 |
CAD (KiCad official)
- Symbol:
STC15W4K48S4-30I-LQFP44 - Footprint:
Package_QFP:LQFP-44_10x10mm_P0.8mm - 3D model: LQFP-44(10x10) (KiCad packages3D, STEP)
- 3D model files:
stc15w4k48s4-30i-lqfp44-etched.step/stc15w4k48s4-30i-lqfp44-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stc15w4k48s4-30i-lqfp44.step/stc15w4k48s4-30i-lqfp44.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STC Micro datasheet (1219 pp, sha256
cc8c299c891646e0, retrieved 2026-10-20, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).