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STC15W4K48S4-30I-LQFP32
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STC Micro Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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STC15W4K48S4-30I-LQFP32
STC Micro · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)
STC15W4K48S4-30I-LQFP32 from STC Micro, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.0 | bidirectional | Standard I/O port P1.0 (PORT1[0]) that also serves as ADC0 analog input channel 0, CCP1 capture/PWM channel 1, and UART2 receive RxD2. |
| 2 | P1.1 | bidirectional | Standard I/O port P1.1 (PORT1[1]) that also serves as ADC1 analog input channel 1, CCP0 capture/PWM channel 0, and UART2 transmit TxD2. |
| 3 | P1.2 | bidirectional | Standard I/O port P1.2 (PORT1[2]) that also serves as ADC2 analog input channel 2, SPI slave select SS, CCP/PCA external pulse input ECI, and comparator output CMPO. |
| 4 | P1.3 | bidirectional | Standard I/O port P1.3 (PORT1[3]) that also serves as ADC3 analog input channel 3 and SPI master-out/slave-in MOSI. |
| 5 | P1.4 | bidirectional | Standard I/O port P1.4 (PORT1[4]) that also serves as ADC4 analog input channel 4 and SPI master-in/slave-out MISO. |
| 6 | P1.5 | bidirectional | Standard I/O port P1.5 (PORT1[5]) that also serves as ADC5 analog input channel 5 and SPI serial clock SCLK. |
| 7 | P1.6 | bidirectional | Standard I/O port P1.6 (PORT1[6]) that also serves as ADC6 input channel 6, UART1 receive RxD_3, system clock output SysClkO_2, XTAL2 crystal amplifier output, and PWM6 output (high-impedance input after power-on, must be configured before use and needs an external pull-up in power-down if high-impedance). |
| 8 | P1.7 | bidirectional | Standard I/O port P1.7 (PORT1[7]) that also serves as ADC7 input channel 7, UART1 transmit TxD_3, XTAL1 crystal amplifier input or external clock input, and PWM7 output (high-impedance input after power-on, must be configured before use and needs an external pull-up in power-down if high-impedance). |
| 9 | P5.4 | bidirectional | Standard I/O port P5.4 (PORT5[4]) that also serves as active-high reset input RST, system clock output SysClkO, SPI slave select SS_3, and comparator negative input CMP- (must be set to high-impedance input when used as CMP-). |
| 10 | Vcc | power_in | Positive supply pin; the series operating voltage is 2.5 V to 5.5 V. |
| 11 | P5.5 | bidirectional | Standard I/O port P5.5 (PORT5[5]) that also serves as comparator positive input CMP+ (must be set to high-impedance input when used as CMP+). |
| 12 | Gnd | power_in | Power supply negative terminal, connected to ground. |
| 13 | P3.0 | bidirectional | Standard I/O port P3.0 (PORT3[0]) that also serves as UART1 receive RxD, external interrupt INT4 (falling edge only, can wake from power-down), and Timer2 clock output T2CLKO; P3.0/P3.1 are used for download/emulation. |
| 14 | P3.1 | bidirectional | Standard I/O port P3.1 (PORT3[1]) that also serves as UART1 transmit TxD and Timer2 external count input T2; P3.0/P3.1 are used for download/emulation. |
| 15 | P3.2 | bidirectional | Standard I/O port P3.2 (PORT3[2]) that also serves as external interrupt INT0, which is rising/falling-edge selectable via IT0 and can wake from power-down. |
| 16 | P3.3 | bidirectional | Standard I/O port P3.3 (PORT3[3]) that also serves as external interrupt INT1, which is rising/falling-edge selectable via IT1 and can wake from power-down. |
| 17 | P3.4 | bidirectional | Standard I/O port P3.4 (PORT3[4]) that also serves as Timer0 external input T0, Timer1 clock output T1CLKO, and CCP/PCA external pulse input ECI_2. |
| 18 | P3.5 | bidirectional | Standard I/O port P3.5 (PORT3[5]) that also serves as Timer1 external input T1, Timer0 clock output T0CLKO, and CCP0_2 capture/PWM channel 0. |
| 19 | P3.6 | bidirectional | Standard I/O port P3.6 (PORT3[6]) that also serves as external interrupt INT2 (falling edge only, can wake from power-down), UART1 receive RxD_2, and CCP1_2 capture/PWM channel 1. |
| 20 | P3.7 | bidirectional | Standard I/O port P3.7 (PORT3[7]) that also serves as external interrupt INT3 (falling edge only, can wake from power-down), UART1 transmit TxD_2, and PWM2 output (high-impedance input after power-on). |
| 21 | P2.0 | bidirectional | Standard I/O port P2.0 (PORT2[0]) that also serves as address bus bit A8 and RSTOUT_LOW, which outputs low after power-on and during reset. |
| 22 | P2.1 | bidirectional | Standard I/O port P2.1 (PORT2[1]) that also serves as address bus bit A9, SPI serial clock SCLK_2, and PWM3 output (high-impedance input after power-on). |
| 23 | P2.2 | bidirectional | Standard I/O port P2.2 (PORT2[2]) that also serves as address bus bit A10, SPI master-in/slave-out MISO_2, and PWM4 output (high-impedance input after power-on). |
| 24 | P2.3 | bidirectional | Standard I/O port P2.3 (PORT2[3]) that also serves as address bus bit A11, SPI master-out/slave-in MOSI_2, and PWM5 output (high-impedance input after power-on). |
| 25 | P2.4 | bidirectional | Standard I/O port P2.4 (PORT2[4]) that also serves as address bus bit A12, CCP/PCA external pulse input ECI_3, SPI slave select SS_2, and PWM fault-stop input PWMFLT. |
| 26 | P2.5 | bidirectional | Standard I/O port P2.5 (PORT2[5]) that also serves as address bus bit A13 and CCP0_3 capture/PWM channel 0. |
| 27 | P2.6 | bidirectional | Standard I/O port P2.6 (PORT2[6]) that also serves as address bus bit A14 and CCP1_3 capture/PWM channel 1. |
| 28 | P2.7 | bidirectional | Standard I/O port P2.7 (PORT2[7]) that also serves as address bus bit A15 and PWM2_2 output (high-impedance input after power-on). |
| 29 | P0.0 | bidirectional | Standard I/O port P0.0 (PORT0[0]) that also serves as address/data bus AD0 and UART3 receive RxD3. |
| 30 | P0.1 | bidirectional | Standard I/O port P0.1 (PORT0[1]) that also serves as address/data bus AD1 and UART3 transmit TxD3. |
| 31 | P0.2 | bidirectional | Standard I/O port P0.2 (PORT0[2]) that also serves as address/data bus AD2 and UART4 receive RxD4. |
| 32 | P0.3 | bidirectional | Standard I/O port P0.3 (PORT0[3]) that also serves as address/data bus AD3 and UART4 transmit TxD4. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STC Micro |
| Package | LQFP-32(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 32 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating temperature (I) (industrial grade) | TA | -40 | 85 | ℃ | 1184 | ||
| Storage temperature | TST | -55 | 125 | ℃ | 1184 | ||
| DC power supply (5V) | VDD - VSS | -0.3 | 5.5 | V | 1184 | ||
| DC power supply (3V) | VDD - VSS | -0.3 | 3.6 | V | 1184 | ||
| Voltage on any pin | -0.3 | V | Printed maximum is VCC + 0.3 | 1184 | |||
| Operating Voltage (5V MCU) | VDD | 3.3 | 5 | 5.5 | V | 1184 | |
| Operating Current (5V MCU) | ICC | 4 | 20 | mA | 5V | 1184 | |
| Input Low (P0,P1,P2,P3) (5V MCU) | VIL1 | 0.8 | V | 5V | 1184 | ||
| Input High (P0,P1,P2,P3) (5V MCU) | VIH1 | 2 | V | 5V | 1184 | ||
| Input High (RESET) (5V MCU) | VIH2 | 2.2 | V | 5V | 1184 | ||
| Sourcing Current for output high (P0,P1,P2,P3)(Quasi-output) (5V MCU) | IOH1 | 200 | 270 | uA | 5V | 1184 | |
| Logic 0 input current (P0,P1,P2,P3) (5V MCU) | IIL | 50 | uA | Vpin=0V | 1184 | ||
| Logic 1 to 0 transition current (P0,P1,P2,P3) (5V MCU) | ITL | 100 | 270 | 600 | uA | Vpin=2.0V | 1184 |
| Operating Voltage (3V MCU) | VDD | 2.4 | 3.3 | 3.6 | V | 1184 | |
| Operating Current (3V MCU) | ICC | 4 | 10 | mA | 3.3V | 1184 | |
| Input Low (P0,P1,P2,P3) (3V MCU) | VIL1 | 0.8 | V | 3.3V | 1184 | ||
| Input High (P0,P1,P2,P3) (3V MCU) | VIH1 | 2 | V | 3.3V | 1184 | ||
| Input High (RESET) (3V MCU) | VIH2 | 2.2 | V | 3.3V | 1184 | ||
| Sourcing Current for output high (P0,P1,P2,P3)(Quasi-output) (3V MCU) | IOH1 | 140 | 170 | uA | 3.3V | 1184 | |
| Logic 0 input current (P0,P1,P2,P3) (3V MCU) | IIL | 8 | 50 | uA | Vpin=0V | 1184 | |
| Logic 1 to 0 transition current (P0,P1,P2,P3) (3V MCU) | ITL | 110 | 600 | uA | Vpin=2.0V | 1184 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the following | 441 |
CAD (KiCad official)
- Symbol:
STC15W4K48S4-30I-LQFP32 - Footprint:
Package_QFP:LQFP-32_7x7mm_P0.8mm - 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files:
stc15w4k48s4-30i-lqfp32-etched.step/stc15w4k48s4-30i-lqfp32-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stc15w4k48s4-30i-lqfp32.step/stc15w4k48s4-30i-lqfp32.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STC Micro datasheet (1219 pp, sha256
cc8c299c891646e0, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).