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STC15W4K32S4-30I-LQFP44
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STC Micro Microcontrollers (MCU/MPU/SOC), LQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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STC15W4K32S4-30I-LQFP44
STC Micro · Microcontrollers (MCU/MPU/SOC) · LQFP-44(10x10)
STC15W4K32S4-30I-LQFP44 from STC Micro, in a LQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0.5 | bidirectional | Standard bidirectional I/O (PORT0[5]); also AD5 address/data bus bit, T3 external counter input, and PWMFLT_2 PWM fault-stop input when PWM2345_S selects it. |
| 2 | P0.6 | bidirectional | Standard bidirectional I/O (PORT0[6]); also AD6 bus bit, T4CLKO timer-4 clock output, and PWM7_2 output that is high-impedance after power-on and must be configured before use. |
| 3 | P0.7 | bidirectional | Standard bidirectional I/O (PORT0[7]); also AD7 bus bit, T4 external input, and PWM6_2 output that is high-impedance after power-on and must be configured before use. |
| 4 | P1.0 | bidirectional | Standard bidirectional I/O (PORT1[0]); also ADC0 analog input, CCP1 capture/PWM output, and RxD2 UART2 receive. |
| 5 | P1.1 | bidirectional | Standard bidirectional I/O (PORT1[1]); also ADC1 analog input, CCP0 capture/PWM output, and TxD2 UART2 transmit. |
| 6 | P4.7 | bidirectional | Standard bidirectional I/O (PORT4[7]); also TxD2_2 UART2 alternate transmit output, selected via S2_S. |
| 7 | P1.2 | bidirectional | Standard bidirectional I/O (PORT1[2]); also ADC2 analog input, SPI SS slave select, ECI CCP/PCA external pulse input, and CMPO comparator output. |
| 8 | P1.3 | bidirectional | Standard bidirectional I/O (PORT1[3]); also ADC3 analog input and SPI MOSI (master out / slave in). |
| 9 | P1.4 | bidirectional | Standard bidirectional I/O (PORT1[4]); also ADC4 analog input and SPI MISO (master in / slave out). |
| 10 | P1.5 | bidirectional | Standard bidirectional I/O (PORT1[5]); also ADC5 analog input and SPI SCLK clock. |
| 11 | P1.6 | bidirectional | Standard bidirectional I/O (PORT1[6]); also ADC6 input, RxD_3 UART1 alternate receive, XTAL2 crystal amplifier output (may float when an external clock drives XTAL1), SysClkO_2 system clock output, and PWM6 output that is high-impedance after power-on. |
| 12 | P1.7 | bidirectional | Standard bidirectional I/O (PORT1[7]); also ADC7 input, TxD_3 UART1 alternate transmit, XTAL1 crystal amplifier input (external clock input when no crystal is used), and PWM7 output that is high-impedance after power-on. |
| 13 | P5.4/RST | bidirectional | Standard I/O (PORT5[4]); also RST high-level reset input, SysClkO system clock output, SS_3 SPI slave select, and CMP- comparator negative input that must be high-impedance when used as CMP-. |
| 14 | Vcc | power_in | Positive power supply; the STC15W4K32S4 series operates from 2.5V to 5.5V. |
| 15 | P5.5 | bidirectional | Standard I/O (PORT5[5]); also CMP+ comparator positive input that must be set to high-impedance input when used as CMP+. |
| 16 | Gnd | power_in | Power supply negative terminal, connected to ground. |
| 17 | P4.0 | bidirectional | Standard I/O (PORT4[0]); alternate SPI function MOSI_3 per the pin map (see review item on the P4.0/P4.1 SPI conflict). |
| 18 | P3.0 | bidirectional | Standard I/O (PORT3[0]); also RxD UART1 receive, INT4 falling-edge external interrupt that can wake power-down mode, and T2CLKO timer-2 clock output. |
| 19 | P3.1 | bidirectional | Standard I/O (PORT3[1]); also TxD UART1 transmit and T2 timer-2 external counter input. |
| 20 | P3.2 | bidirectional | Standard I/O (PORT3[2]); also INT0 external interrupt, which is rising/falling edge when IT0=0 and falling-edge only when IT0=1, and which supports power-down wake-up. |
| 21 | P3.3 | bidirectional | Standard I/O (PORT3[3]); also INT1 external interrupt, which is rising/falling edge when IT1=0 and falling-edge only when IT1=1, and which supports power-down wake-up. |
| 22 | P3.4 | bidirectional | Standard I/O (PORT3[4]); also T0 timer-0 external input, T1CLKO timer-1 clock output, and ECI_2 CCP/PCA external pulse input. |
| 23 | P3.5 | bidirectional | Standard I/O (PORT3[5]); also T1 timer-1 external input, T0CLKO timer-0 clock output, and CCP0_2 capture/PWM channel 0. |
| 24 | P3.6 | bidirectional | Standard I/O (PORT3[6]); also INT2 falling-edge-only external interrupt that supports power-down wake-up, RxD_2 UART1 alternate receive, and CCP1_2 capture/PWM channel 1. |
| 25 | P3.7 | bidirectional | Standard I/O (PORT3[7]); also INT3 falling-edge-only external interrupt that supports power-down wake-up, TxD_2 UART1 alternate transmit, and PWM2 output that is high-impedance after power-on. |
| 26 | P4.1 | bidirectional | Standard I/O (PORT4[1]); alternate SPI function MISO_3 per the pin map (see review item on the P4.0/P4.1 SPI conflict). |
| 27 | P4.2 | bidirectional | Standard I/O (PORT4[2]); also WR external data memory write strobe and PWM5_2 output that is high-impedance after power-on. |
| 28 | P4.3 | bidirectional | Standard I/O (PORT4[3]); also SCLK_3 SPI clock signal. |
| 29 | P4.4 | bidirectional | Standard I/O (PORT4[4]); also RD external data memory read strobe and PWM4_2 output that is high-impedance after power-on. |
| 30 | P2.0 | bidirectional | Standard I/O (PORT2[0]); also A8 address bus bit 8 and RSTOUT_LOW, which drives low after power-on and during reset. |
| 31 | P2.1 | bidirectional | Standard I/O (PORT2[1]); also A9 address bus bit, SCLK_2 SPI clock alternate, and PWM3 output that is high-impedance after power-on. |
| 32 | P2.2 | bidirectional | Standard I/O (PORT2[2]); also A10 address bus bit, MISO_2 SPI alternate, and PWM4 output that is high-impedance after power-on. |
| 33 | P2.3 | bidirectional | Standard I/O (PORT2[3]); also A11 address bus bit, MOSI_2 SPI alternate, and PWM5 output that is high-impedance after power-on. |
| 34 | P2.4 | bidirectional | Standard I/O (PORT2[4]); also A12 address bus bit, ECI_3 CCP/PCA external pulse input, SS_2 SPI slave select, and PWMFLT PWM fault-stop input. |
| 35 | P2.5 | bidirectional | Standard I/O (PORT2[5]); also A13 address bus bit and CCP0_3 capture/PWM channel 0. |
| 36 | P2.6 | bidirectional | Standard I/O (PORT2[6]); also A14 address bus bit and CCP1_3 capture/PWM channel 1. |
| 37 | P2.7 | bidirectional | Standard I/O (PORT2[7]); also A15 address bus bit and PWM2_2 output that is high-impedance after power-on. |
| 38 | P4.5 | bidirectional | Standard I/O (PORT4[5]); also ALE address latch enable and PWM3_2 output that is high-impedance after power-on. |
| 39 | P4.6 | bidirectional | Standard I/O (PORT4[6]); also RxD2_2 UART2 alternate receive input. |
| 40 | P0.0 | bidirectional | Standard I/O (PORT0[0]); also AD0 address/data bus bit and RxD3 UART3 receive. |
| 41 | P0.1 | bidirectional | Standard I/O (PORT0[1]); also AD1 address/data bus bit and TxD3 UART3 transmit. |
| 42 | P0.2 | bidirectional | Standard I/O (PORT0[2]); also AD2 address/data bus bit and RxD4 UART4 receive. |
| 43 | P0.3 | bidirectional | Standard I/O (PORT0[3]); also AD3 address/data bus bit and TxD4 UART4 transmit. |
| 44 | P0.4 | bidirectional | Standard I/O (PORT0[4]); also AD4 address/data bus bit and T3CLKO timer-3 clock output. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STC Micro |
| Package | LQFP-44(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 44 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature | TST | -55 | 125 | ℃ | 1184 | ||
| Operating temperature (I) | TA | -40 | 85 | ℃ | Grade (I) row | 1184 | |
| DC power supply (5V) | VDD - VSS | -0.3 | 5.5 | V | 1184 | ||
| DC power supply (3V) | VDD - VSS | -0.3 | 3.6 | V | 1184 | ||
| Voltage on any pin | -0.3 | V | Max printed as VCC + 0.3 V | 1184 | |||
| Operating Voltage (5V MCU table) | VDD | 3.3 | 5 | 5.5 | V | 1184 | |
| Operating Current (5V MCU table) | ICC | 4 | 20 | mA | 5V | 1184 | |
| Input Low (P0,P1,P2,P3) | VIL1 | 0.8 | V | 5V | 1184 | ||
| Input High (P0,P1,P2,P3) | VIH1 | 2 | V | 5V | 1184 | ||
| Input High (RESET) | VIH2 | 2.2 | V | 5V | 1184 | ||
| Sourcing Current for output high (P0,P1,P2,P3) (Quasi-output) | IOH1 | 200 | 270 | uA | 5V | 1184 | |
| Logic 0 input current (P0,P1,P2,P3) | IIL | 50 | uA | Vpin=0V | 1184 | ||
| Logic 1 to 0 transition current (P0,P1,P2,P3) | ITL | 100 | 270 | 600 | uA | Vpin=2.0V | 1184 |
| Operating Voltage (3V MCU table) | VDD | 2.4 | 3.3 | 3.6 | V | 1184 | |
| Operating Current (3V MCU table) | ICC | 4 | 10 | mA | 3.3V | 1184 | |
| Sourcing Current for output high (P0,P1,P2,P3) (Quasi-output) | IOH1 | 140 | 170 | uA | 3.3V | 1184 | |
| Logic 0 input current (P0,P1,P2,P3) | IIL | 8 | 50 | uA | Vpin=0V | 1184 | |
| Logic 1 to 0 transition current (P0,P1,P2,P3) | ITL | 110 | 600 | uA | Vpin=2.0V | 1184 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the following | 441 |
CAD (KiCad official)
- Symbol:
STC15W4K32S4-30I-LQFP44 - Footprint:
Package_QFP:LQFP-44_10x10mm_P0.8mm - 3D model: LQFP-44(10x10) (KiCad packages3D, STEP)
- 3D model files:
stc15w4k32s4-30i-lqfp44-etched.step/stc15w4k32s4-30i-lqfp44-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stc15w4k32s4-30i-lqfp44.step/stc15w4k32s4-30i-lqfp44.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STC Micro datasheet (1219 pp, sha256
cc8c299c891646e0, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).