# STC15L2K32S2-28I-LQFP32

**STC Micro** · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)

STC15L2K32S2-28I-LQFP32 from STC Micro, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.0/ADC0/CCP1/RxD2 | bidirectional | Standard bidirectional I/O port P1.0 (PORT1[0]) with alternate functions ADC input channel 0, CCP1 capture/compare/PWM channel 1, and UART2 receive RxD2. |
| 2 | P1.1/ADC1/CCP0/TxD2 | bidirectional | Standard bidirectional I/O port P1.1 (PORT1[1]) with alternate functions ADC input channel 1, CCP0 capture/compare/PWM channel 0, and UART2 transmit TxD2. |
| 3 | P1.2/ADC2/SS/ECI | bidirectional | Standard bidirectional I/O port P1.2 (PORT1[2]) with alternate functions ADC input channel 2, SPI slave select SS, and CCP/PCA external counter pulse input ECI. |
| 4 | P1.3/ADC3/MOSI | bidirectional | Standard bidirectional I/O port P1.3 (PORT1[3]) with alternate functions ADC input channel 3 and SPI master-out/slave-in MOSI. |
| 5 | P1.4/ADC4/MISO | bidirectional | Standard bidirectional I/O port P1.4 (PORT1[4]) with alternate functions ADC input channel 4 and SPI master-in/slave-out MISO. |
| 6 | P1.5/ADC5/SCLK | bidirectional | Standard bidirectional I/O port P1.5 (PORT1[5]) with alternate functions ADC input channel 5 and SPI serial clock SCLK. |
| 7 | P1.6/ADC6/RxD_3/XTAL2 | bidirectional | Standard bidirectional I/O port P1.6 (PORT1[6]) with alternate functions ADC input channel 6, UART1 receive RxD_3, and XTAL2 (inverting amplifier output for an external crystal; may float when an external clock drives XTAL1). |
| 8 | P1.7/ADC7/TxD_3/XTAL1 | bidirectional | Standard bidirectional I/O port P1.7 (PORT1[7]) with alternate functions ADC input channel 7, UART1 transmit TxD_3, and XTAL1 (inverting amplifier input for an external crystal, or external clock source input when no crystal is used). |
| 9 | P5.4/RST/MCLKO/SS_3 | bidirectional | Standard bidirectional I/O port P5.4 (PORT5[4]) which is I/O by default out of the factory; it can be set via STC-ISP as RST reset input (high-level reset) or used for MCLKO master clock output (MCLK/1, /2, /4) or SPI slave select SS_3. |
| 10 | Vcc | power_in | Positive power supply; the STC15L2K series operates from 2.4 V to 3.6 V. |
| 11 | P5.5 | bidirectional | Standard bidirectional I/O port P5.5 (PORT5[5]) with no alternate function listed for the LQFP32 package. |
| 12 | Gnd | power_in | Power supply negative terminal, connected to ground. |
| 13 | P3.0/RxD/INT4/T2CLKO | bidirectional | Standard bidirectional I/O port P3.0 (PORT3[0]) with alternate functions UART1 receive RxD, external interrupt INT4 (falling edge only, supports power-down wake-up), and Timer 2 clock output T2CLKO. |
| 14 | P3.1/TxD/T2 | bidirectional | Standard bidirectional I/O port P3.1 (PORT3[1]) with alternate functions UART1 transmit TxD and external input of Timer/Counter 2 (T2). |
| 15 | P3.2/INT0 | bidirectional | Standard bidirectional I/O port P3.2 (PORT3[2]) with external interrupt INT0, which is rising/falling-edge capable (falling edge only if IT0 is set) and supports power-down wake-up. |
| 16 | P3.3/INT1 | bidirectional | Standard bidirectional I/O port P3.3 (PORT3[3]) with external interrupt INT1, which is rising/falling-edge capable (falling edge only if IT1 is set) and supports power-down wake-up. |
| 17 | P3.4/T0/T1CLKO/ECI_2 | bidirectional | Standard bidirectional I/O port P3.4 (PORT3[4]) with alternate functions Timer 0 external input T0, Timer 1 clock output T1CLKO, and CCP/PCA external pulse input ECI_2. |
| 18 | P3.5/T1/T0CLKO/CCP0_2 | bidirectional | Standard bidirectional I/O port P3.5 (PORT3[5]) with alternate functions Timer 1 external input T1, Timer 0 clock output T0CLKO, and CCP0 channel on CCP0_2. |
| 19 | P3.6/INT2/RxD_2/CCP1_2 | bidirectional | Standard bidirectional I/O port P3.6 (PORT3[6]) with alternate functions external interrupt INT2 (falling edge only, supports power-down wake-up), UART1 receive RxD_2, and CCP1 channel on CCP1_2. |
| 20 | P3.7/INT3/TxD_2/CCP2/CCP2_2 | bidirectional | Standard bidirectional I/O port P3.7 (PORT3[7]) with alternate functions external interrupt INT3 (falling edge only, supports power-down wake-up), UART1 transmit TxD_2, and CCP2 channel on CCP2/CCP2_2. |
| 21 | P2.0/A8/RSTOUT_LOW | bidirectional | Standard bidirectional I/O port P2.0 (PORT2[0]) with address bus bit A8 for external memory and RSTOUT_LOW, which outputs low during power-up and reset. |
| 22 | P2.1/A9/SCLK_2 | bidirectional | Standard bidirectional I/O port P2.1 (PORT2[1]) with address bus bit A9 for external memory and SPI serial clock SCLK_2. |
| 23 | P2.2/A10/MISO_2 | bidirectional | Standard bidirectional I/O port P2.2 (PORT2[2]) with address bus bit A10 for external memory and SPI master-in/slave-out MISO_2. |
| 24 | P2.3/A11/MOSI_2 | bidirectional | Standard bidirectional I/O port P2.3 (PORT2[3]) with address bus bit A11 for external memory and SPI master-out/slave-in MOSI_2. |
| 25 | P2.4/A12/ECI_3/SS_2 | bidirectional | Standard bidirectional I/O port P2.4 (PORT2[4]) with address bus bit A12 for external memory, CCP/PCA external pulse input ECI_3, and SPI slave select SS_2. |
| 26 | P2.5/A13/CCP0_3 | bidirectional | Standard bidirectional I/O port P2.5 (PORT2[5]) with address bus bit A13 for external memory and CCP0 capture/compare/PWM channel on CCP0_3. |
| 27 | P2.6/A14/CCP1_3 | bidirectional | Standard bidirectional I/O port P2.6 (PORT2[6]) with address bus bit A14 for external memory and CCP1 capture/compare/PWM channel on CCP1_3. |
| 28 | P2.7/A15/CCP2_3 | bidirectional | Standard bidirectional I/O port P2.7 (PORT2[7]) with address bus bit A15 for external memory and CCP2 capture/compare/PWM channel on CCP2_3. |
| 29 | P0.0/AD0 | bidirectional | Port P0.0 (PORT0[0]) can be configured as quasi-bidirectional with weak pull-up (default after reset), push-pull, input-only or open-drain, and is the AD0 low address/data bus bit when the external bus is used. |
| 30 | P0.1/AD1 | bidirectional | Port P0.1 (PORT0[1]) can be configured as quasi-bidirectional with weak pull-up (default after reset), push-pull, input-only or open-drain, and is the AD1 low address/data bus bit when the external bus is used. |
| 31 | P0.2/AD2 | bidirectional | Port P0.2 (PORT0[2]) can be configured as quasi-bidirectional with weak pull-up (default after reset), push-pull, input-only or open-drain, and is the AD2 low address/data bus bit when the external bus is used. |
| 32 | P0.3/AD3 | bidirectional | Port P0.3 (PORT0[3]) can be configured as quasi-bidirectional with weak pull-up (default after reset), push-pull, input-only or open-drain, and is the AD3 low address/data bus bit when the external bus is used. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STC Micro |
| Package | LQFP-32(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 32 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Voltage (3V MCU) | VDD | 2.4 | 3.3 | 3.6 | V |  | 1030 |
| Operating Current | ICC |  | 4 | 10 | mA | 3.3V | 1030 |
| Input Low (P0,P1,P2,P3) | VIL1 |  |  | 0.8 | V | 3.3V | 1030 |
| Input High (P0,P1,P2,P3) | VIH1 | 2 |  |  | V | 3.3V | 1030 |
| Input High (RESET) | VIH2 | 2.2 |  |  | V | 3.3V | 1030 |
| Sourcing Current for output high (P0,P1,P2,P3) (Quasi-output) | IOH1 | 140 | 170 |  | uA | 3.3V | 1030 |
| Logic 0 input current (P0,P1,P2,P3) | IIL |  | 8 | 50 | uA | Vpin=0V; 3.3V | 1030 |
| Logic 1 to 0 transition current (P0,P1,P2,P3) | ITL |  | 110 | 600 | uA | Vpin=2.0V; 3.3V | 1030 |
| Storage temperature | TST | -55 |  | 125 | ℃ |  | 1030 |
| Operating temperature (I) | TA | -40 |  | 85 | ℃ | Industrial grade (I suffix of this MPN) | 1030 |
| DC power supply (3V) | VDD - VSS | -0.3 |  | 3.6 | V | 3V MCU | 1030 |
| Voltage on any pin |  | -0.3 |  |  | V | Max printed as VCC + 0.3 | 1030 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC |  | Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the | 437 |

## CAD (KiCad official)

- Symbol: `STC15L2K32S2-28I-LQFP32`
- Footprint: `Package_QFP:LQFP-32_7x7mm_P0.8mm`
- 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files: `stc15l2k32s2-28i-lqfp32-etched.step` / `stc15l2k32s2-28i-lqfp32-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stc15l2k32s2-28i-lqfp32.step` / `stc15l2k32s2-28i-lqfp32.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STC Micro datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586172177259368448) (1097 pp, sha256 `8b798668f36be5ce`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/stc15l2k32s2-28i-lqfp32-datasheet.pdf)