Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

STB24N60M2

STMicroelectronics · MOSFETs · D2PAK

STB24N60M2 from STMicroelectronics, in a D2PAK. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate terminal; gate-source voltage is limited to ±25 V (Table 1).
2 D passive Drain terminal, electrically connected to the tab; drain-source voltage 600 V and continuous drain current 18 A at TC = 25 °C (Table 1).
3 S passive Source terminal; source-drain diode rated 18 A continuous and 72 A pulsed (Table 7).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package D2PAK
Category Triode/MOS Tube/Transistor
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-source voltage VDS 600 V 2
Gate-source voltage VGS -25 25 V 2
Drain current (continuous) ID 18 A TC = 25 °C 2
Drain current (continuous) ID 12 A TC = 100 °C 2
Drain current (pulsed) IDM 72 A Pulse width limited by safe operating area 2
Total power dissipation PTOT 150 W TC = 25 °C 2
Peak diode recovery voltage slope dv/dt 15 V/ns ISD ≤ 18 A, di/dt ≤ 400 A/μs, VDS (peak) < V(BR)DSS, VDD = 400 V 2
MOSFET dv/dt ruggedness dv/dt 50 V/ns VDS = 480 V 2
Storage temperature range Tstg -55 150 °C 2
Avalanche current, repetitive or not-repetitive IAR 3.5 A Pulse width limited by TJ max. 2
Single pulse avalanche energy EAS 180 mJ Starting TJ = 25 °C, ID = IAR, VDD = 50 V 2
Thermal resistance, junction-to-case RthJC 0.83 °C/W 2
Thermal resistance, junction-to-ambient RthJA 30 °C/W D2PAK; mounted on a standard 1 inch² area of FR-4 PCB with 2-oz copper 2
Drain-source breakdown voltage V(BR)DSS 600 V ID = 1 mA, VGS = 0 V 3
Zero gate voltage drain current IDSS 1 µA VGS = 0 V, VDS = 600 V 3
Zero gate voltage drain current IDSS 100 µA VGS = 0 V, VDS = 600 V, TC = 125 °C 3
Gate body leakage current IGSS -10 10 µA VDS = 0 V, VGS = ±25 V 3
Gate threshold voltage VGS(th) 2 3 4 V VDS = VGS, ID = 250 µA 3
Static drain-source on-resistance RDS(on) 168 190 mΩ VGS = 10 V, ID = 9 A 3
Source-drain current ISD 18 A 4
Source-drain current (pulsed) ISDM 72 A 4
Forward on voltage VSD 1.6 V ISD = 18 A, VGS = 0 V 4

CAD (KiCad official)

  • Symbol: STB24N60M2
  • Footprint: Package_TO_SOT_SMD:TO-263-2
  • 3D model: D2PAK (KiCad packages3D, STEP)
  • 3D model files: stb24n60m2-etched.step / stb24n60m2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stb24n60m2.step / stb24n60m2.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (22 pp, sha256 fd2390933a1c5a2f, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF