# ST730MR

**STMicroelectronics** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5L

ST730MR from STMicroelectronics, in a SOT-23-5L. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | output | Regulated output voltage adjustable from 1.2 V to VIN - VDROP maximum, capable of sourcing up to 300 mA. |
| 2 | GND | power_in | Ground reference connection. |
| 3 | VIN | power_in | Input power supply voltage, operating range 2.5 V to 28 V. |
| 4 | ADJ | input | External resistor divider connection for adjustable output voltage setting; reference voltage 1.2 V (VADJ) typical at 25°C. |
| 5 | EN | input | Enable control input pin, logic low (≤0.35 V) disables output, logic high (≥1.2 V) enables active operation; do not leave floating. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOT-23-5L |
| Category | Power Management (PMIC) |
| Pins | 5 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating input voltage | VIN | 2.5 |  | 28 | V |  | 7 |
| Reference voltage accuracy | VADJ | 1.194 |  | 1.206 | % | TJ = 25 °C | 7 |
| Reference voltage accuracy | VADJ | -2 |  | 2 | % | -40 °C < TJ < +125 °C | 7 |
| Adjust pin leakage current | IADJ |  |  | 100 | nA |  | 7 |
| Static line regulation | ΔVOUT |  | 0.005 | 0.05 | %/V | VIN = 2.5 V to 28 V | 7 |
| Static load regulation | ΔVOUT |  | 0.001 | 0.003 | %/mA | IOUT = 1 mA to 300 mA | 7 |
| Quiescent current | IQ |  | 5 | 10 | µA | IOUT = 0 mA | 7 |
| Quiescent current | IQ |  | 120 | 240 | µA | IOUT = 300 mA | 7 |
| Standby current |  |  | 0.35 | 1 | µA | VIN = 2.5 V to 28 V, VEN = GND | 7 |
| Enable input logic low | VEN |  |  | 0.35 | V |  | 7 |
| Enable input logic high | VEN | 1.2 |  |  | V |  | 7 |
| Enable pin current | IEN |  |  | 100 | nA | VEN = VIN | 7 |
| DC input voltage | VIN | -0.3 |  | 30 | V |  | 5 |
| DC output voltage | VOUT | -0.3 |  |  | V |  | 5 |
| Enable pin voltage | VEN | -0.3 |  | 30 | V |  | 5 |
| Adjust pin voltage | VADJ | -0.3 |  | 2.5 | V |  | 5 |
| Storage temperature range | TST | -65 |  | 150 | °C |  | 5 |
| Operating temperature range | TOP | -40 |  | 125 | °C |  | 5 |
| Human body model ESD | HBM | -2 |  | 2 | kV |  | 5 |
| Charged device model ESD | CDM | -500 |  | 500 | V |  | 5 |
| Thermal resistance junction-ambient | RthJA |  | 190 |  | °C/W | 4-layer (2S2P) JEDEC test board per JESD 51-7 | 5 |
| Thermal resistance junction-case | RthJC |  | 75 |  | °C/W |  | 5 |
| Input capacitor minimum value | CIN | 0.1 |  |  | µF |  | 8 |
| Output capacitor minimum value | COUT | 0.47 |  |  | µF | X5R/X7R ceramic | 8 |
| Output capacitor ESR range | ESR | 5 |  | 500 | mΩ |  | 8 |

## CAD (KiCad official)

- Symbol: `ST730MR`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5L (KiCad packages3D, STEP)
- 3D model files: `st730mr-etched.step` / `st730mr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `st730mr.step` / `st730mr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603011049633701888) (23 pp, sha256 `d57671a28e22aa41`, retrieved 2026-09-23, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/st730mr-datasheet.pdf)