component

ST72F324BJ6T6

Public Made by Adom

by adom

STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersst72f324bj6t6factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers st72f324bj6t6: viewers · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Initial commit: component/st72f324bj6t6 · Ray 1d ago
st72f324bj6t6-etched.glb st72f324bj6t6: factory component page (tier=lcsc) · Ray 1d ago
st72f324bj6t6-etched.step st72f324bj6t6: factory component page (tier=lcsc) · Ray 1d ago
st72f324bj6t6-hero.glb st72f324bj6t6: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
st72f324bj6t6-hero.overlay.json Publish 0.1.0 · Ray 1d ago
st72f324bj6t6.glb Publish 0.1.0 · Ray 1d ago
st72f324bj6t6.kicad_mod Publish 0.1.0 · Ray 1d ago
st72f324bj6t6.kicad_sym Publish 0.1.0 · Ray 1d ago
st72f324bj6t6.lbr Publish 0.1.0 · Ray 1d ago
st72f324bj6t6.step Publish 0.1.0 · Ray 1d ago

ST72F324BJ6T6

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-44(10x10)

ST72F324BJ6T6 from STMicroelectronics, in a LQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE1/RDI bidirectional Port E1 bidirectional I/O (CMOS 0.3VDD/0.7VDD with input trigger), alternate function SCI receive data input.
2 PB0 bidirectional Port B0 I/O with external interrupt source ei2; negative current injection is not allowed on this pin on 8/16 Kbyte Flash devices.
3 PB1 bidirectional Port B1 general-purpose I/O with external interrupt source ei2.
4 PB2 bidirectional Port B2 general-purpose I/O with external interrupt source ei2.
5 PB3 bidirectional Port B3 general-purpose I/O with external interrupt source ei2.
6 PB4 bidirectional Port B4 I/O with external interrupt source ei3 and 20 mA high-sink capability (N-buffer only).
7 PD0/AIN0 bidirectional Port D0 I/O that doubles as ADC analog input 0; when used as analog input it must be configured as input, no pull-up, no interrupt.
8 PD1/AIN1 bidirectional Port D1 I/O that doubles as ADC analog input 1; when used as analog input it must be configured as input, no pull-up, no interrupt.
9 PD2/AIN2 bidirectional Port D2 I/O that doubles as ADC analog input 2; when used as analog input it must be configured as input, no pull-up, no interrupt.
10 PD3/AIN3 bidirectional Port D3 I/O that doubles as ADC analog input 3; when used as analog input it must be configured as input, no pull-up, no interrupt.
11 PD4/AIN4 bidirectional Port D4 I/O that doubles as ADC analog input 4; when used as analog input it must be configured as input, no pull-up, no interrupt.
12 PD5/AIN5 bidirectional Port D5 I/O that doubles as ADC analog input 5; when used as analog input it must be configured as input, no pull-up, no interrupt.
13 VAREF power_in Analog reference voltage for the ADC; all available VDD and VREF pins must be connected to the supply voltage.
14 VSSA power_in Analog ground voltage for the ADC; all VSS and VSSA pins must be connected to ground.
15 PF0/MCO/AIN8 bidirectional Port F0 I/O with external interrupt ei1; alternate functions are main clock output (fCPU) and ADC analog input 8.
16 PF1/BEEP bidirectional Port F1 I/O with 20 mA high-sink capability and external interrupt ei1; alternate function is beep signal output.
17 PF2 bidirectional Port F2 I/O with 20 mA high-sink capability and external interrupt ei1.
18 PF4/OCMP1_A/AIN10 bidirectional Port F4 I/O; alternate functions are Timer A output compare 1 and ADC analog input 10.
19 PF6/ICAP1_A bidirectional Port F6 I/O with 20 mA high-sink capability; alternate function is Timer A input capture 1.
20 PF7/EXTCLK_A bidirectional Port F7 I/O with 20 mA high-sink capability; alternate function is Timer A external clock source.
21 VDD_0 power_in Digital main supply voltage; operating range is 3.8 to 5.5 V and all VDD pins must be connected to the supply.
22 VSS_0 power_in Digital ground voltage; all VSS pins must be connected to ground.
23 PC0/OCMP2_B/AIN12 bidirectional Port C0 I/O; alternate functions are Timer B output compare 2 and ADC analog input 12.
24 PC1/OCMP1_B/AIN13 bidirectional Port C1 I/O; alternate functions are Timer B output compare 1 and ADC analog input 13.
25 PC2/ICAP2_B bidirectional Port C2 I/O with 20 mA high-sink capability; alternate function is Timer B input capture 2.
26 PC3/ICAP1_B bidirectional Port C3 I/O with 20 mA high-sink capability; alternate function is Timer B input capture 1.
27 PC4/MISO/ICCDATA bidirectional Port C4 I/O; alternate functions are SPI master-in/slave-out data and ICC data input.
28 PC5/MOSI/AIN14 bidirectional Port C5 I/O; alternate functions are SPI master-out/slave-in data and ADC analog input 14.
29 PC6/SCK/ICCCLK bidirectional Port C6 I/O; alternate functions are SPI serial clock and ICC clock output.
30 PC7/SS/AIN15 bidirectional Port C7 I/O; alternate functions are SPI slave select (active low) and ADC analog input 15.
31 PA3 bidirectional Port A3 I/O with 20 mA high-sink capability and external interrupt ei0.
32 VDD_1 power_in Digital main supply voltage; all VDD pins must be connected to the supply.
33 VSS_1 power_in Digital ground voltage; all VSS pins must be connected to ground.
34 PA4 bidirectional Port A4 I/O with 20 mA high-sink capability.
35 PA5 bidirectional Port A5 I/O with 20 mA high-sink capability.
36 PA6 bidirectional Port A6 I/O implemented as a true open-drain pad (no protection diode to VDD) with 20 mA high-sink capability.
37 PA7 bidirectional Port A7 I/O implemented as a true open-drain pad (no protection diode to VDD) with 20 mA high-sink capability.
38 VPP/ICCSEL input Must be tied low in normal operation; in Flash programming mode it is the VPP programming voltage input, and high voltage must not be applied to ROM devices.
39 RESET bidirectional Reset I/O pin with top-priority non-maskable interrupt function.
40 VSS_2 power_in Digital ground voltage; all VSS pins must be connected to ground.
41 OSC2 output Resonator oscillator inverter output for connection of a crystal or ceramic resonator.
42 OSC1 input External clock input or resonator oscillator inverter input.
43 VDD_2 power_in Digital main supply voltage; all VDD pins must be connected to the supply.
44 PE0/TDO bidirectional Port E0 I/O; alternate function is SCI transmit data output.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-44(10x10)
Category Embedded Processors & Controllers
Pins 44

CAD (KiCad official)

  • Symbol: ST72F324BJ6T6
  • Footprint: Package_QFP:LQFP-44_10x10mm_P0.8mm
  • 3D model: LQFP-44(10x10) (KiCad packages3D, STEP)
  • 3D model files: st72f324bj6t6-etched.step / st72f324bj6t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); st72f324bj6t6.step / st72f324bj6t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (198 pp, sha256 5f25336efa7e0074, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF