main
Download ZIP Propose a change
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
Name Last commit message Last updated
docs st1s10phr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
page.json st1s10phr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 12h ago
README.md st1s10phr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 16d ago
st1s10phr-etched.fit.json st1s10phr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
st1s10phr-etched.glb st1s10phr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
st1s10phr-etched.step st1s10phr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
st1s10phr.glb fix footprint: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm -> TI_SO-PowerPAD-8 (ep_dropped, 8 pins; datasheet EP 3.1x2.41mm, land 2.41x3.1mm (Δ0.0mm)) · Ray 1mo ago
st1s10phr.kicad_mod fix footprint: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm -> TI_SO-PowerPAD-8 (ep_dropped, 8 pins; datasheet EP 3.1x2.41mm, land 2.41x3.1mm (Δ0.0mm)) · Ray 1mo ago
st1s10phr.kicad_sym Publish 0.1.0 · Ray 1mo ago
st1s10phr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 0 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
st1s10phr.step fix footprint: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm -> TI_SO-PowerPAD-8 (ep_dropped, 8 pins; datasheet EP 3.1x2.41mm, land 2.41x3.1mm (Δ0.0mm)) · Ray 1mo ago

ST1S10PHR

STMicroelectronics · DC-DC Converters · SOIC-8-EP

ST1S10PHR from STMicroelectronics, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN_A power_in Analog input supply voltage. Tie to the VIN supply source. Absolute maximum -0.3 to 20 V.
2 INH input Inhibit pin, active low. Connect to VIN_A if not used to enable the regulator. Absolute maximum -0.3 V to VIN_A.
3 VFB input Feedback voltage input for external resistor divider used to program VOUT from 0.8 V up to 0.85*VIN_SW. Absolute maximum -0.3 to 2.5 V, FB current -1 to +1 mA.
4 AGND power_in Analog ground return for the control circuitry. Connect to the ground plane, kept separate from PGND at the reference point.
5 SYNC input Synchronization and frequency select. Tie to GND for 900 kHz free-running operation, or drive with an external clock from 400 kHz to 1.2 MHz. Absolute maximum -0.3 to 6 V.
6 VIN_SW power_in Power input supply voltage for the internal switching power stage. Tie to the VIN power supply source, decoupled with a 4.7 µF capacitor. Absolute maximum -0.3 to 20 V.
7 SW output Switching node output for the external inductor of the step-down converter. Absolute maximum -0.3 to 20 V, up to 3 A output current capability.
8 PGND power_in Power ground return for the internal low-side switch. Connect to the ground plane close to the input capacitor.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SOIC-8-EP
Category PMIC
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • ST1S10PHR
  • ST1S10PHRPUR

CAD (KiCad official)

  • Symbol: ST1S10PHR
  • Footprint: Package_SO:TI_SO-PowerPAD-8
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)
  • 3D model files: st1s10phr-etched.step / st1s10phr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); st1s10phr.step / st1s10phr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
st1s10phr.step 123 KB You want the bare part, or you mark your own boards.
st1s10phr-etched.step 1.9 MB You want the part with ST1S10PHR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 486 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (26 pp, sha256 6d16dc400027720c, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF