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ST10F276Z5T3

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STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ST10F276Z5T3

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-144(20x20)

ST10F276Z5T3 from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P6.0 bidirectional Port 6 bit 0: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function Chip Select 0 output.
2 P6.1 bidirectional Port 6 bit 1: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function Chip Select 1 output.
3 P6.2 bidirectional Port 6 bit 2: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function Chip Select 2 output.
4 P6.3 bidirectional Port 6 bit 3: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function Chip Select 3 output.
5 P6.4 bidirectional Port 6 bit 4: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function Chip Select 4 output.
6 P6.5 bidirectional Port 6 bit 5: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate functions HOLD (external master hold request input) or SCLK1 (SSC1 master clock output/slave clock input).
7 P6.6 bidirectional Port 6 bit 6: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate functions HLDA (hold acknowledge output) or MTSR1 (SSC1 master-transmitter/slave-receiver).
8 P6.7 bidirectional Port 6 bit 7: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate functions BREQ (bus request output) or MRST1 (SSC1 master-receiver/slave-transmitter).
9 P8.0 bidirectional Port 8 bit 0: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate functions XPWM0 (PWM1 channel 0 output) or CC16IO (CAPCOM2 capture/compare).
10 P8.1 bidirectional Port 8 bit 1: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate functions XPWM1 (PWM1 channel 1 output) or CC17IO (CAPCOM2 capture/compare).
11 P8.2 bidirectional Port 8 bit 2: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate functions XPWM2 (PWM1 channel 2 output) or CC18IO (CAPCOM2 capture/compare).
12 P8.3 bidirectional Port 8 bit 3: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate functions XPWM3 (PWM1 channel 3 output) or CC19IO (CAPCOM2 capture/compare).
13 P8.4 bidirectional Port 8 bit 4: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function CC20IO (CAPCOM2 capture/compare).
14 P8.5 bidirectional Port 8 bit 5: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function CC21IO (CAPCOM2 capture/compare).
15 P8.6 bidirectional Port 8 bit 6: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate functions RxD1 (ASC1 data input asynchronous or I/O synchronous) or CC22IO (CAPCOM2 capture/compare).
16 P8.7 bidirectional Port 8 bit 7: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate functions TxD1 (ASC1 clock/data output asynchronous/synchronous) or CC23IO (CAPCOM2 capture/compare).
17 VDD power_in Digital supply voltage +5V ±10% during normal operation, idle and power-down modes.
18 VSS power_in Digital ground.
19 P7.0 bidirectional Port 7 bit 0: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function POUT0 (PWM0 channel 0 output).
20 P7.1 bidirectional Port 7 bit 1: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function POUT1 (PWM0 channel 1 output).
21 P7.2 bidirectional Port 7 bit 2: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function POUT2 (PWM0 channel 2 output).
22 P7.3 bidirectional Port 7 bit 3: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function POUT3 (PWM0 channel 3 output).
23 P7.4 bidirectional Port 7 bit 4: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function CC28IO (CAPCOM2 capture/compare).
24 P7.5 bidirectional Port 7 bit 5: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function CC29IO (CAPCOM2 capture/compare).
25 P7.6 bidirectional Port 7 bit 6: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function CC30IO (CAPCOM2 capture/compare).
26 P7.7 bidirectional Port 7 bit 7: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function CC31IO (CAPCOM2 capture/compare).
27 P5.0 input Port 5 bit 0: 16-bit input-only with Schmitt-trigger characteristics, selectable TTL/CMOS threshold; analog input channel AN0 or timer input.
28 P5.1 input Port 5 bit 1: 16-bit input-only with Schmitt-trigger characteristics, selectable TTL/CMOS threshold; analog input channel AN1 or timer input.
29 P5.2 input Port 5 bit 2: 16-bit input-only with Schmitt-trigger characteristics, selectable TTL/CMOS threshold; analog input channel AN2 or timer input.
30 P5.3 input Port 5 bit 3: 16-bit input-only with Schmitt-trigger characteristics, selectable TTL/CMOS threshold; analog input channel AN3 or timer input.
31 P5.4 input Port 5 bit 4: 16-bit input-only with Schmitt-trigger characteristics, selectable TTL/CMOS threshold; analog input channel AN4 or timer input.
32 P5.5 input Port 5 bit 5: 16-bit input-only with Schmitt-trigger characteristics, selectable TTL/CMOS threshold; analog input channel AN5 or timer input.
33 P5.6 input Port 5 bit 6: 16-bit input-only with Schmitt-trigger characteristics, selectable TTL/CMOS threshold; analog input channel AN6 or timer input.
34 P5.7 input Port 5 bit 7: 16-bit input-only with Schmitt-trigger characteristics, selectable TTL/CMOS threshold; analog input channel AN7 or timer input.
35 P5.8 input Port 5 bit 8: 16-bit input-only with Schmitt-trigger characteristics, selectable TTL/CMOS threshold; analog input channel AN8 or timer input.
36 P5.9 input Port 5 bit 9: 16-bit input-only with Schmitt-trigger characteristics, selectable TTL/CMOS threshold; analog input channel AN9 or timer input.
37 VAREF passive A/D converter reference voltage and analog supply for analog circuit biasing.
38 VAGND passive A/D converter reference and analog ground.
39 P5.10 input Port 5 bit 10: 16-bit input-only with Schmitt-trigger characteristics; analog input channel AN10 or alternate function T6EUD (GPT2 timer T6 external up/down control input).
40 P5.11 input Port 5 bit 11: 16-bit input-only with Schmitt-trigger characteristics; analog input channel AN11 or alternate function T5EUD (GPT2 timer T5 external up/down control input).
41 P5.12 input Port 5 bit 12: 16-bit input-only with Schmitt-trigger characteristics; analog input channel AN12 or alternate function T6IN (GPT2 timer T6 count input).
42 P5.13 input Port 5 bit 13: 16-bit input-only with Schmitt-trigger characteristics; analog input channel AN13 or alternate function T5IN (GPT2 timer T5 count input).
43 P5.14 input Port 5 bit 14: 16-bit input-only with Schmitt-trigger characteristics; analog input channel AN14 or alternate function T4EUD (GPT1 timer T4 external up/down control input).
44 P5.15 input Port 5 bit 15: 16-bit input-only with Schmitt-trigger characteristics; analog input channel AN15 or alternate function T2EUD (GPT1 timer T2 external up/down control input).
45 VSS power_in Digital ground.
46 VDD power_in Digital supply voltage +5V ±10% during normal operation, idle and power-down modes.
47 P2.0 bidirectional Port 2 bit 0: 16-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function CC0IO (CAPCOM capture/compare).
48 P2.1 bidirectional Port 2 bit 1: 16-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function CC1IO (CAPCOM capture/compare).
49 P2.2 bidirectional Port 2 bit 2: 16-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function CC2IO (CAPCOM capture/compare).
50 P2.3 bidirectional Port 2 bit 3: 16-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function CC3IO (CAPCOM capture/compare).
51 P2.4 bidirectional Port 2 bit 4: 16-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function CC4IO (CAPCOM capture/compare).
52 P2.5 bidirectional Port 2 bit 5: 16-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function CC5IO (CAPCOM capture/compare).
53 P2.6 bidirectional Port 2 bit 6: 16-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function CC6IO (CAPCOM capture/compare).
54 P2.7 bidirectional Port 2 bit 7: 16-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function CC7IO (CAPCOM capture/compare).
55 VSS power_in Digital ground.
56 V18 power_out 1.8V decoupling pin; 10nF typical (max 100nF) decoupling capacitor required between this pin and nearest VSS.
57 P2.8 bidirectional Port 2 bit 8: 16-bit bidirectional I/O with selectable TTL/CMOS threshold; alternate functions CC8IO (CAPCOM capture/compare) or EX0IN (fast external interrupt 0 input).
58 P2.9 bidirectional Port 2 bit 9: 16-bit bidirectional I/O with selectable TTL/CMOS threshold; alternate functions CC9IO (CAPCOM capture/compare) or EX1IN (fast external interrupt 1 input).
59 P2.10 bidirectional Port 2 bit 10: 16-bit bidirectional I/O with selectable TTL/CMOS threshold; alternate functions CC10IO (CAPCOM capture/compare) or EX2IN (fast external interrupt 2 input).
60 P2.11 bidirectional Port 2 bit 11: 16-bit bidirectional I/O with selectable TTL/CMOS threshold; alternate functions CC11IO (CAPCOM capture/compare) or EX3IN (fast external interrupt 3 input).
61 P2.12 bidirectional Port 2 bit 12: 16-bit bidirectional I/O with selectable TTL/CMOS threshold; alternate functions CC12IO (CAPCOM capture/compare) or EX4IN (fast external interrupt 4 input).
62 P2.13 bidirectional Port 2 bit 13: 16-bit bidirectional I/O with selectable TTL/CMOS threshold; alternate functions CC13IO (CAPCOM capture/compare) or EX5IN (fast external interrupt 5 input).
63 P2.14 bidirectional Port 2 bit 14: 16-bit bidirectional I/O with selectable TTL/CMOS threshold; alternate functions CC14IO (CAPCOM capture/compare) or EX6IN (fast external interrupt 6 input).
64 P2.15 bidirectional Port 2 bit 15: 16-bit bidirectional I/O with selectable TTL/CMOS threshold; alternate functions CC15IO (CAPCOM capture/compare), EX7IN (fast external interrupt 7 input), or T7IN (CAPCOM2 timer T7 count input).
65 P3.0 bidirectional Port 3 bit 0: 15-bit (P3.14 missing) bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function T0IN (CAPCOM1 timer T0 count input).
66 P3.1 bidirectional Port 3 bit 1: 15-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function T6OUT (GPT2 timer T6 toggle latch output).
67 P3.2 bidirectional Port 3 bit 2: 15-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function CAPIN (GPT2 register CAPREL capture input).
68 P3.3 bidirectional Port 3 bit 3: 15-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function T3OUT (GPT1 timer T3 toggle latch output).
69 P3.4 bidirectional Port 3 bit 4: 15-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function T3EUD (GPT1 timer T3 external up/down control input).
70 P3.5 bidirectional Port 3 bit 5: 15-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function T4IN (GPT1 timer T4 count/gate/reload/capture input).
71 VSS power_in Digital ground.
72 VDD power_in Digital supply voltage +5V ±10% during normal operation, idle and power-down modes.
73 P3.6 bidirectional Port 3 bit 6: 15-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function T3IN (GPT1 timer T3 count/gate input).
74 P3.7 bidirectional Port 3 bit 7: 15-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function T2IN (GPT1 timer T2 count/gate/reload/capture input).
75 P3.8 bidirectional Port 3 bit 8: 15-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function MRST0 (SSC0 master-receiver/slave-transmitter I/O).
76 P3.9 bidirectional Port 3 bit 9: 15-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function MTSR0 (SSC0 master-transmitter/slave-receiver O/I).
77 P3.10 bidirectional Port 3 bit 10: 15-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function TxD0 (ASC0 clock/data output asynchronous/synchronous).
78 P3.11 bidirectional Port 3 bit 11: 15-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function RxD0 (ASC0 data input asynchronous or I/O synchronous).
79 P3.12 bidirectional Port 3 bit 12: 15-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate functions BHE (external memory high byte enable) or WRH (external memory high byte write strobe).
80 P3.13 bidirectional Port 3 bit 13: 15-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function SCLK0 (SSC0 master clock output/slave clock input).
81 P3.15 bidirectional Port 3 bit 15: 15-bit bidirectional I/O with selectable TTL/CMOS threshold and programmable push-pull/open-drain output; alternate function CLKOUT (system clock output with programmable divider).
82 VDD power_in Digital supply voltage +5V ±10% during normal operation, idle and power-down modes.
83 VSS power_in Digital ground.
84 RPD passive Timing pin for return from interruptible power-down mode and synchronous/asynchronous reset selection.
85 P4.0 bidirectional Port 4 bit 0: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; alternate function A16 (segment address line).
86 P4.1 bidirectional Port 4 bit 1: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; alternate function A17 (segment address line).
87 P4.2 bidirectional Port 4 bit 2: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; alternate function A18 (segment address line).
88 P4.3 bidirectional Port 4 bit 3: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; alternate function A19 (segment address line).
89 P4.4 bidirectional Port 4 bit 4: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and push-pull/open-drain output; alternate functions A20 (segment address line), CAN2_RxD (CAN2 receive data input), or SCL (I2C serial clock).
90 P4.5 bidirectional Port 4 bit 5: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and push-pull/open-drain output; alternate functions A21 (segment address line), CAN1_RxD (CAN1 receive data input), or CAN2_RxD (CAN2 receive data input).
91 P4.6 bidirectional Port 4 bit 6: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and push-pull/open-drain output; alternate functions A22 (segment address line), CAN1_TxD (CAN1 transmit data output), or CAN2_TxD (CAN2 transmit data output).
92 P4.7 bidirectional Port 4 bit 7: 8-bit bidirectional I/O with selectable TTL/CMOS threshold and push-pull/open-drain output; alternate functions A23 (most significant segment address line), CAN2_TxD (CAN2 transmit data output), or SDA (I2C serial data).
93 VDD power_in Digital supply voltage +5V ±10% during normal operation, idle and power-down modes.
94 VSS power_in Digital ground.
95 RD output External memory read strobe output; activated for every external instruction or data read access.
96 WR/WRL output External memory write strobe output; WR-mode activated for every external data write access; WRL-mode for low byte writes on 16-bit bus or every write on 8-bit bus.
97 READY input Ready input with programmable active level; when enabled, inactive level during external memory access forces wait-state insertion until pin returns to active level.
98 ALE output Address latch enable output; provides address line latch command for external addressing or multiplexed bus mode.
99 EA/VSTBY input External access enable input; low level during/after reset forces program start from external memory, high level forces internal memory startup; 4.5-5.5V during operation, 4.0-6.0V for standby bias.
100 P0L.0 bidirectional Port 0 lower bit 0: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode data bit D0, multiplexed bus mode address/data AD0.
101 P0L.1 bidirectional Port 0 lower bit 1: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode data bit D1, multiplexed bus mode address/data AD1.
102 P0L.2 bidirectional Port 0 lower bit 2: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode data bit D2, multiplexed bus mode address/data AD2.
103 P0L.3 bidirectional Port 0 lower bit 3: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode data bit D3, multiplexed bus mode address/data AD3.
104 P0L.4 bidirectional Port 0 lower bit 4: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode data bit D4, multiplexed bus mode address/data AD4.
105 P0L.5 bidirectional Port 0 lower bit 5: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode data bit D5, multiplexed bus mode address/data AD5.
106 P0L.6 bidirectional Port 0 lower bit 6: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode data bit D6, multiplexed bus mode address/data AD6.
107 P0L.7 bidirectional Port 0 lower bit 7: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode data bit D7, multiplexed bus mode address/data AD7.
108 P0H.0 bidirectional Port 0 upper bit 0: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode data bit D8, multiplexed bus mode address/data AD8.
109 VDD power_in Digital supply voltage +5V ±10% during normal operation, idle and power-down modes.
110 VSS power_in Digital ground.
111 P0H.1 bidirectional Port 0 upper bit 1: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode data bit D9, multiplexed bus mode address/data AD9.
112 P0H.2 bidirectional Port 0 upper bit 2: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode data bit D10, multiplexed bus mode address/data AD10.
113 P0H.3 bidirectional Port 0 upper bit 3: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode data bit D11, multiplexed bus mode address/data AD11.
114 P0H.4 bidirectional Port 0 upper bit 4: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode data bit D12, multiplexed bus mode address/data AD12.
115 P0H.5 bidirectional Port 0 upper bit 5: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode data bit D13, multiplexed bus mode address/data AD13.
116 P0H.6 bidirectional Port 0 upper bit 6: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode data bit D14, multiplexed bus mode address/data AD14.
117 P0H.7 bidirectional Port 0 upper bit 7: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode data bit D15, multiplexed bus mode address/data AD15.
118 P1L.0 bidirectional Port 1 lower bit 0: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode address bit A0; analog input channel AN16 with priority.
119 P1L.1 bidirectional Port 1 lower bit 1: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode address bit A1; analog input channel AN17 with priority.
120 P1L.2 bidirectional Port 1 lower bit 2: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode address bit A2; analog input channel AN18 with priority.
121 P1L.3 bidirectional Port 1 lower bit 3: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode address bit A3; analog input channel AN19 with priority.
122 P1L.4 bidirectional Port 1 lower bit 4: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode address bit A4; analog input channel AN20 with priority.
123 P1L.5 bidirectional Port 1 lower bit 5: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode address bit A5; analog input channel AN21 with priority.
124 P1L.6 bidirectional Port 1 lower bit 6: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode address bit A6; analog input channel AN22 with priority.
125 P1L.7 bidirectional Port 1 lower bit 7: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode address bit A7; analog input channel AN23 with priority.
126 VDD power_in Digital supply voltage +5V ±10% during normal operation, idle and power-down modes.
127 VSS power_in Digital ground.
128 P1H.0 bidirectional Port 1 upper bit 0: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode address bit A8; alternate function CC24IO (CAPCOM2 capture/compare).
129 P1H.1 bidirectional Port 1 upper bit 1: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode address bit A9; alternate function CC25IO (CAPCOM2 capture/compare).
130 P1H.2 bidirectional Port 1 upper bit 2: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode address bit A10.
131 P1H.3 bidirectional Port 1 upper bit 3: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode address bit A11.
132 P1H.4 bidirectional Port 1 upper bit 4: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode address bit A12; alternate function CC24IO (CAPCOM2 capture/compare).
133 P1H.5 bidirectional Port 1 upper bit 5: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode address bit A13; alternate function CC25IO (CAPCOM2 capture/compare).
134 P1H.6 bidirectional Port 1 upper bit 6: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode address bit A14; alternate function CC26IO (CAPCOM2 capture/compare).
135 P1H.7 bidirectional Port 1 upper bit 7: 8-bit bidirectional I/O with selectable TTL/CMOS threshold; demultiplexed bus mode address bit A15; alternate function CC27IO (CAPCOM2 capture/compare).
136 VDD power_in Digital supply voltage +5V ±10% during normal operation, idle and power-down modes.
137 XTAL2 output Main oscillator amplifier circuit output; leave unconnected when driving XTAL1 directly from external source.
138 XTAL1 input Main oscillator amplifier circuit input and/or external clock input for CPU clock generation.
139 VSS power_in Digital ground.
140 RSTIN input Reset input with CMOS Schmitt-trigger characteristics; low level for specified duration resets device; internal pull-up permits power-on reset with capacitor to VSS.
141 RSTOUT output Internal reset indication output; driven low during hardware, software, or watchdog timer reset until EINIT instruction execution.
142 NMI input Non-maskable interrupt input; high-to-low transition vectors CPU to NMI trap routine; must be pulled high externally if not used.
143 XTAL3 input 32kHz oscillator amplifier circuit input; must use crystal oscillator, not external clock source; tie to ground if not used.
144 XTAL4 output 32kHz oscillator amplifier circuit output; leave open when 32kHz oscillator not used.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-144(20x20)
Category Embedded Processors & Controllers
Pins 144

CAD (KiCad official)

  • Symbol: ST10F276Z5T3
  • Footprint: Package_QFP:LQFP-144_20x20mm_P0.5mm
  • 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
  • 3D model files: st10f276z5t3-etched.step / st10f276z5t3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); st10f276z5t3.step / st10f276z5t3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (240 pp, sha256 7787cf3fb6171d2c, retrieved 2026-10-05, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF