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SST26VF016B-80E

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Microchip Tech Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SST26VF016B-80E

Microchip Tech · Pre-ordered Chips · SOIC-8

SST26VF016B-80E from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CE# input Chip Enable: the device is enabled by a high-to-low transition and CE# must remain low for the duration of any command sequence.
2 SO/SIO1 bidirectional Serial Data Output in SPI mode (data shifted out on the falling edge of SCK, default state after Power-on Reset) or serial data I/O 1 in Quad I/O mode.
3 WP#/SIO2 bidirectional Write-Protect, used with the WPEN and IOC bits in the Configuration register to prohibit writes to the Block Protection register and only effective in SPI single-bit and dual-bit Read mode, or serial data I/O 2 in Quad I/O mode.
4 VSS power_in Ground.
5 SI/SIO0 bidirectional Serial Data Input in SPI mode (inputs latched on the rising edge of SCK, default state after Power-on Reset) or serial data I/O 0 in Quad I/O mode.
6 SCK input Serial Clock providing timing of the serial interface, with commands, addresses and input data latched on the rising edge and output data shifted out on the falling edge.
7 HOLD#/SIO3 bidirectional Hold, which temporarily stops serial communication while the device is selected, works only in SPI single-bit and dual-bit Read mode and must be tied high when not in use, or serial data I/O 3 in Quad I/O mode.
8 VDD power_in Power supply voltage, 2.3V-3.6V for single-voltage read and write operations (2.7V-3.6V for 104 MHz operation).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Temperature under bias -55 125 °C 43
Storage temperature -65 150 °C 43
DC voltage on any pin to ground potential -0.5 V upper limit VDD+0.5V 43
Transient voltage on any pin to ground potential -2 V <20 ns; upper limit VDD+2.0V 43
Package power dissipation capability 1 W TA = +25°C 43
Surface mount solder reflow temperature 260 °C for 10 seconds 43
VDD supply voltage operating range VDD 2.3 3.6 V Industrial, Industrial Plus and Extended ranges 43
Ambient temperature, Industrial range -40 85 °C VDD 2.3V-3.6V 43
Ambient temperature, Industrial Plus range -40 105 °C VDD 2.3V-3.6V 43
Ambient temperature, Extended range -40 125 °C VDD 2.3V-3.6V; max operating frequency 80 MHz 43
VDD Min to Read Operation TPU-READ 100 µs 43
VDD Min to Write Operation TPU-WRITE 100 µs 43
Power-Down Duration TPD 100 ms 43
VDD Off Time VOFF 0.3 V 0V recommended 43
Read Current IDDR 20 mA VDD = VDD maximum, CE# = 0.1 VDD/0.9 VDD @80 MHz, SO = open 45
Read Current IDDR1 8 15 mA VDD = VDD maximum, CE# = 0.1 VDD/0.9 VDD @40 MHz, SO = open 45
Program and Erase Current IDDW 25 mA VDD maximum 45
Standby Current ISB1 15 45 µA CE# = VDD, VIN = VDD or VSS @+105°C 45
Standby Current ISB2 80 µA CE# = VDD, VIN = VDD or VSS @+125°C 45
Deep Power-Down Current IDPD 8 25 µA CE# = VDD, VIN = VDD or VSS 45
Input Leakage Current ILI 2 µA VIN = GND to VDD, VDD = VDD maximum 45
Output Leakage Current ILO 2 µA VOUT = GND to VDD, VDD = VDD maximum 45
Input Low Voltage VIL 0.8 V VDD = VDD minimum 45
Output Low Voltage VOL 0.2 V IOL = 100 µA, VDD = VDD minimum 45
Pin Output Capacitance COUT 8 pF VOUT = 0V, TA = +25°C, F = 1 MHz 45
Input Capacitance CIN 6 pF VIN = 0V, TA = +25°C, F = 1 MHz 45
Endurance NEND 100000 Cycles JEDEC Standard A117 45
Data Retention TDR 100 Years JEDEC Standard A103 45
Sector Erase TSE 25 ms VDD 2.3V-3.6V 46
Block Erase TBE 25 ms VDD 2.3V-3.6V 46
Chip Erase TSCE 50 ms VDD 2.3V-3.6V 46
Page Program TPP 1.5 ms VDD 2.3V-3.6V; estimate for typical conditions less than 256 bytes 46
Program Security ID TPSID 1.5 ms VDD 2.3V-3.6V 46
Write Suspend Latency TWS 25 µs VDD 2.3V-3.6V 46
Write Protection Enable Bit Latency TWPEN 25 ms VDD 2.3V-3.6V 46
Serial Clock Frequency (80 MHz column) FCLK 80 MHz VDD 2.3V-3.6V 47
Serial Clock Period (80 MHz column) TCLK 12.5 ns VDD 2.3V-3.6V 47
Serial Clock High Time (80 MHz column) TSCKH 5.5 ns VDD 2.3V-3.6V 47
Serial Clock Low Time (80 MHz column) TSCKL 5.5 ns VDD 2.3V-3.6V 47
CE# Active Setup Time (80 MHz column) TCES 5 ns relative to SCK; VDD 2.3V-3.6V 47
CE# Active Hold Time (80 MHz column) TCEH 5 ns relative to SCK; VDD 2.3V-3.6V 47
CE# Not Active Setup Time (80 MHz column) TCHS 5 ns relative to SCK; VDD 2.3V-3.6V 47
CE# Not Active Hold Time (80 MHz column) TCHH 5 ns relative to SCK; VDD 2.3V-3.6V 47
CE# High Time (80 MHz column) TCPH 12.5 ns VDD 2.3V-3.6V 47
CE# High to High-Z Output (80 MHz column) TCHZ 12.5 ns VDD 2.3V-3.6V 47
HOLD# Low Setup Time (80 MHz column) THLS 5 ns VDD 2.3V-3.6V 47
HOLD# High Setup Time (80 MHz column) THHS 5 ns VDD 2.3V-3.6V 47
HOLD# Low Hold Time (80 MHz column) THLH 5 ns VDD 2.3V-3.6V 47
HOLD# High Hold Time (80 MHz column) THHH 5 ns VDD 2.3V-3.6V 47
HOLD# Low-to-High-Z Output (80 MHz column) THZ 8 ns VDD 2.3V-3.6V 47
HOLD# High-to-Low-Z Output (80 MHz column) TLZ 8 ns VDD 2.3V-3.6V 47
Data In Setup Time (80 MHz column) TDS 3 ns VDD 2.3V-3.6V 47
Data In Hold Time (80 MHz column) TDH 4 ns VDD 2.3V-3.6V 47
Output Valid from SCK (80 MHz column) TV 8 ns 30 pF load; printed as 8/5 at 30 pF/10 pF 47
Reset to Read (non-data operation) TR(O) 20 ns 48
Reset Recovery from Program or Suspend TR(P) 100 µs 48
Reset Recovery from Erase TR(E) 1 ms 48

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] A A2 51

CAD (KiCad official)

  • Symbol: SST26VF016B-80E
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: sst26vf016b-80e-etched.step / sst26vf016b-80e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sst26vf016b-80e.step / sst26vf016b-80e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (84 pp, sha256 aad66521b828d469, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF