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SST26VF016B-104I

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Microchip Tech NOR FLASH, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SST26VF016B-104I

Microchip Tech · NOR FLASH · SOIC-8

SST26VF016B-104I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CE# input Chip Enable: the device is enabled by a high-to-low transition on CE#, which must remain low for the duration of any command sequence or of the write command/data input sequence.
2 SO/SIO1 bidirectional Serial Data Output (SO) in SPI mode, shifted out on the falling edge of SCK and the default state after Power-on Reset; serves as Serial Data I/O 1 (SIO1) when the EQIO command configures Quad I/O mode.
3 WP#/SIO2 bidirectional Write-Protect, used with the WPEN and IOC bits to prohibit writes to the Block Protection register, working only in SPI single-bit and dual-bit Read mode; serves as SIO2 in Quad I/O mode.
4 VSS power_in Ground reference for the device.
5 SI/SIO0 bidirectional Serial Data Input (SI) in SPI mode, latched on the rising edge of SCK and the default state after Power-on Reset; serves as Serial Data I/O 0 (SIO0) in Quad I/O mode.
6 SCK input Serial Clock providing the timing of the serial interface; commands, addresses and input data are latched on the rising edge while output data shift out on the falling edge.
7 HOLD#/SIO3 bidirectional Hold, which temporarily stops serial communication while the device is selected and works only in SPI single-bit and dual-bit Read mode; it must be tied high when not in use, and serves as SIO3 in Quad I/O mode.
8 VDD power_in Power supply voltage input; the features list gives 2.7V-3.6V or 2.3V-3.6V for read and write operation.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD 2.3 3.6 V Operating range, Table 6-1 (Industrial) 43
Ambient temperature (Industrial) TA -40 85 °C Industrial range, Table 6-1 43
Temperature under bias -55 125 °C 43
Storage temperature -65 150 °C 43
DC voltage on any pin to ground -0.5 0.5 V vs VDD Printed as -0.5V to VDD+0.5V 43
Transient voltage on any pin to ground (<20 ns) -2 2 V vs VDD <20 ns; printed as -2.0V to VDD+2.0V 43
Package power dissipation capability 1 W TA = +25°C 43
Surface mount solder reflow temperature 260 °C 10 seconds 43
Read current IDDR 20 mA VDD = VDD maximum, CE# = 0.1 VDD/0.9 VDD @80 MHz, SO = open 45
Read current IDDR1 8 15 mA VDD = VDD maximum, CE# = 0.1 VDD/0.9 VDD @40 MHz, SO = open 45
Program and Erase current IDDW 25 mA VDD maximum 45
Standby current ISB1 15 45 µA CE# = VDD, VIN = VDD or VSS @+105°C 45
Deep Power-Down current IDPD 8 25 µA CE# = VDD, VIN = VDD or VSS 45
Input leakage current ILI 2 µA VIN = GND to VDD, VDD = VDD maximum 45
Output leakage current ILO 2 µA VOUT = GND to VDD, VDD = VDD maximum 45
Input Low Voltage VIL 0.8 V VDD = VDD minimum 45
Input High Voltage VIH 0.7 VDD VDD = VDD maximum; printed as 0.7 VDD 45
Output Low Voltage VOL 0.2 V IOL = 100 µA, VDD = VDD minimum 45
Output High Voltage VOH -0.2 V vs VDD IOH = -100 µA, VDD = VDD minimum; printed as VDD-0.2 45
Output Pin Capacitance COUT 8 pF TA = +25°C, F = 1 MHz; VOUT = 0V 45
Input Capacitance CIN 6 pF TA = +25°C, F = 1 MHz; VIN = 0V 45
Endurance NEND 100000 Cycles JEDEC Standard A117 45
Data Retention TDR 100 Years JEDEC Standard A103 45
Sector Erase time TSE 25 ms VDD = 2.3V-3.6V 46
Block Erase time TBE 25 ms VDD = 2.3V-3.6V 46
Chip Erase time TSCE 50 ms VDD = 2.3V-3.6V 46
Page Program time TPP 1.5 ms VDD = 2.3V-3.6V 46
Program Security ID time TPSID 1.5 ms VDD = 2.3V-3.6V 46
Write Suspend latency TWS 25 µs VDD = 2.3V-3.6V 46
Write Protection Enable Bit latency TWPEN 25 ms VDD = 2.3V-3.6V 46
VDD Min to Read Operation TPU-READ 100 µs Recommended system power-up timing 43
VDD Min to Write Operation TPU-WRITE 100 µs Recommended system power-up timing 43
Power-Down Duration TPD 100 ms Recommended system power-down timing 43
VDD Off Time VOFF 0.3 V 0V recommended 43
Serial Clock Frequency FCLK 104 MHz VDD = 2.3V-3.6V; 104 MHz column (max 104 MHz for 2.7V-3.6V) 47
Serial Clock Period TCLK 9.6 ns 104 MHz column 47
Serial Clock High Time TSCKH 4.5 ns 104 MHz column 47
Serial Clock Low Time TSCKL 4.5 ns 104 MHz column 47
Serial Clock Rise Time (slew rate) TSCKR 0.1 V/ns 104 MHz column 47
Serial Clock Fall Time (slew rate) TSCKF 0.1 V/ns 104 MHz column 47
CE# Active Setup Time TCES 5 ns Relative to SCK; 104 MHz column 47
CE# Active Hold Time TCEH 5 ns Relative to SCK; 104 MHz column 47
CE# Not Active Setup Time TCHS 5 ns Relative to SCK; 104 MHz column 47
CE# Not Active Hold Time TCHH 5 ns Relative to SCK; 104 MHz column 47
CE# High Time TCPH 12 ns 104 MHz column 47
CE# High to High-Z Output TCHZ 12 ns 104 MHz column 47
HOLD# Low Setup Time THLS 5 ns 104 MHz column 47
HOLD# High Setup Time THHS 5 ns 104 MHz column 47
HOLD# Low Hold Time THLH 5 ns 104 MHz column 47
HOLD# High Hold Time THHH 5 ns 104 MHz column 47
HOLD# Low-to-High-Z Output THZ 8 ns 104 MHz column 47
HOLD# High-to-Low-Z Output TLZ 8 ns 104 MHz column 47
Data In Setup Time TDS 3 ns 104 MHz column 47
Data In Hold Time TDH 4 ns 104 MHz column 47
Output Valid from SCK TV 8 ns CL = 30 pF; printed 8/5 for 30 pF/10 pF (10 pF value 5 ns not recorded) 47
Reset to Read (non-data operation) TR(O) 20 ns 48
Reset Recovery from Program or Suspend TR(P) 100 µs 48
Reset Recovery from Erase TR(E) 1 ms 48

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] A A2 51

CAD (KiCad official)

  • Symbol: SST26VF016B-104I
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: sst26vf016b-104i-etched.step / sst26vf016b-104i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sst26vf016b-104i.step / sst26vf016b-104i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (84 pp, sha256 aad66521b828d469, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF