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SSP7785-5.0V

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Shanghai Siproin Microelectronics SSP7785 5 0V Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, ESOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs ssp7785-5-0v: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json add symbol pin "9" for the exposed thermal pad: the footprint carries the pad and the symbol had none, so it reached no net (vendor string 'ESOP-8' denotes an exposed pad) · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 10d ago
README.md ssp7785-5-0v: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 14d ago
ssp7785-5-0v-etched.fit.json ssp7785-5-0v: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
ssp7785-5-0v-etched.glb ssp7785-5-0v: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
ssp7785-5-0v-etched.step ssp7785-5-0v: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
ssp7785-5-0v.glb fix footprint: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm (3d refresh; body regenerated from the footprint F.Fab outline) · Ray 1mo ago
ssp7785-5-0v.kicad_mod Publish 0.1.0 · Ray 1mo ago
ssp7785-5-0v.kicad_sym add symbol pin "9" for the exposed thermal pad: the footprint carries the pad and the symbol had none, so it reached no net (vendor string 'ESOP-8' denotes an exposed pad) · Ray 1mo ago
ssp7785-5-0v.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 8 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
ssp7785-5-0v.step fix footprint: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm (3d refresh; body regenerated from the footprint F.Fab outline) · Ray 1mo ago

SSP7785-5.0V

Shanghai Siproin Microelectronics · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · ESOP-8

SSP7785-5.0V from Shanghai Siproin Microelectronics, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected Not connected. High-voltage isolation pin (referenced as HV pin no.1 in ESD spec, so must remain floating for clearance to the input node).
2 GND power_in Ground connection. Return for input and output decoupling capacitors.
3 VOUT power_out Regulated 5.0 V output (±5% over line/load/temperature), 10 mA guaranteed output current. Requires a 22 µF or larger MLCC capacitor from VOUT to GND for stability.
4 NC unconnected Not connected.
5 NC unconnected Not connected.
6 NC unconnected Not connected.
7 VIN power_in High-voltage supply input, 50 V to 450 V DC operating range (absolute max 650 V). Requires a 2.2 µF capacitor from VIN to GND placed close to the pin.
8 NC unconnected Not connected.

Key specifications

Parameter Value
Manufacturer Shanghai Siproin Microelectronics
Package ESOP-8
Category PMIC
Pins 8

CAD (KiCad official)

  • Symbol: SSP7785-5.0V
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm
  • 3D model: ESOP-8 (KiCad packages3D, STEP)
  • 3D model files: ssp7785-5-0v-etched.step / ssp7785-5-0v-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ssp7785-5-0v.step / ssp7785-5-0v.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
ssp7785-5-0v.step 193 KB You want the bare part, or you mark your own boards.
ssp7785-5-0v-etched.step 2.1 MB You want the part with SSP7785-5.0V already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 508 faces against 63 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Shanghai Siproin Microelectronics datasheet (8 pp, sha256 613a512bb5c0de48, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF