# SSP6202P252MR

**Shanghai Siproin Microelectronics** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23

SSP6202P252MR from Shanghai Siproin Microelectronics, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | power_out | Regulated 2.5V output (±2% accuracy, up to 150mA at Vin-Vout=1V), with a 1uF tantalum or 6.8uF ceramic output capacitor recommended. |
| 2 | VIN | power_in | Supply input, rated up to 15V operating (absolute maximum 18V, -0.3V minimum), with a 1uF input capacitor. |
| 3 | VSS | power_in | Ground pin of the regulator. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Shanghai Siproin Microelectronics |
| Package | SOT-23 |
| Category | Power Management (PMIC) |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage accuracy (Vout×0.98 to Vout×1.02); printed as tolerance ±2% in Features | Vout | -2 |  | 2 | % | Vin=Vout+1V, 1.0mA≤Iout≤30mA | 4 |
| Input voltage | Vin |  |  | 15 | V |  | 4 |
| Supply current | Iss1 |  |  | 2 | μA |  | 4 |
| Line regulation |  |  | 0.05 | 0.2 | %/V | 1.6V≤Vin≤8V, Iout=100mA | 4 |
| Load regulation | △Vout |  |  | 30 | mV | Vin=Vout+1V, 1.0mA≤Iout≤100mA | 4 |
| Output voltage temperature coefficient (printed ±100) |  | -100 |  | 100 | Ppm/℃ | Iout=30mA, 0℃≤Ta≤70℃ | 4 |
| Dropout voltage (2.0 < Vout ≤ 3.0 band, applies to 2.5V) | Vdif |  | 0.12 | 0.14 | V | Iout=80 mA | 4 |
| Supply voltage (absolute maximum) | Vin | -0.3 |  | 18 | V |  | 3 |
| Operating temperature |  | -40 |  | 85 | ℃ |  | 3 |
| Storage temperature |  | -40 |  | 125 | ℃ |  | 3 |
| Output current | Iout |  | 150 |  | mA | Vin-Vout=1V | 4 |
| Power supply rejection ratio | PSRR |  | 40 |  | dB | F=1KHz, Vin=Vout+1V | 4 |

## CAD (KiCad official)

- Symbol: `SSP6202P252MR`
- Footprint: `Package_TO_SOT_SMD:SOT-23`
- 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files: `ssp6202p252mr-etched.step` / `ssp6202p252mr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ssp6202p252mr.step` / `ssp6202p252mr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Shanghai Siproin Microelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588911775433965568) (6 pp, sha256 `2c2a621890b85abc`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ssp6202p252mr-datasheet.pdf)