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docs ssp61cc4002mr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
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package.json Publish 0.2.0 · Ray 1mo ago
page.json ssp61cc4002mr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 19h ago
README.md ssp61cc4002mr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 19d ago
ssp61cc4002mr-etched.fit.json ssp61cc4002mr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
ssp61cc4002mr-etched.glb ssp61cc4002mr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
ssp61cc4002mr-etched.step ssp61cc4002mr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
ssp61cc4002mr.glb Publish 0.1.0 · Ray 1mo ago
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ssp61cc4002mr.step Publish 0.1.0 · Ray 1mo ago

SSP61CC4002MR

Shanghai Siproin Microelectronics · Supervisor and Reset ICs · SOT-23

SSP61CC4002MR from Shanghai Siproin Microelectronics, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUT output CMOS push-pull output. Drives high (Hi-Z relative to VIN - see output table) when VDD > VDET(+); pulls low to VSS when VDD ≤ VDET(-). Output sink current IOL ≥ 0.5 mA at VOUT=0.2V with VIN=2V.
2 GND power_in Ground / VSS reference.
3 VIN power_in Supply voltage input and monitored voltage. Absolute maximum 8.0V; operating range 0.7V to 10V (per Electrical Characteristics). Also serves as the sensed node for the internal comparator.

Key specifications

Parameter Value
Manufacturer Shanghai Siproin Microelectronics
Package SOT-23
Category PMIC
Pins 3

Ordering variants

Same part, different packaging or reel option.

  • SSP61CC4002MRM
  • SSP61CC4002MRN

CAD (KiCad official)

  • Symbol: SSP61CC4002MR
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: ssp61cc4002mr-etched.step / ssp61cc4002mr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ssp61cc4002mr.step / ssp61cc4002mr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
ssp61cc4002mr.step 59 KB You want the bare part, or you mark your own boards.
ssp61cc4002mr-etched.step 2.5 MB You want the part with SSP61CC4002MR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 606 faces against 69 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Shanghai Siproin Microelectronics datasheet (10 pp, sha256 49887c43b8edefc9, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF