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SSP1220
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Shanghai Siproin Microelectronics Analog To Digital Converters (ADCs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSSP1220
Shanghai Siproin Microelectronics · Analog To Digital Converters (ADCs) · TSSOP-16
SSP1220 from Shanghai Siproin Microelectronics, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCLK | input | Serial clock input for the SPI interface. |
| 2 | CS | input | Chip select, active low; connect to DGND if not used. |
| 3 | CLK | input | External clock source pin (0.5 to 4.5 MHz, 4.096 MHz nominal); connect to DGND if not used. |
| 4 | DGND | power_in | Digital ground. |
| 5 | AVSS | power_in | Negative analog power supply. |
| 6 | AIN3/REFN1 | input | Analog input 3 or negative reference input 1, with an internal low-side power switch connected between AIN3/REFN1 and AVSS. |
| 7 | AIN2 | input | Analog input 2. |
| 8 | REFN0 | input | Negative reference input 0. |
| 9 | REFP0 | input | Positive reference input 0. |
| 10 | AIN1 | input | Analog input 1. |
| 11 | AIN0/REFP1 | input | Analog input 0 or positive reference input 1. |
| 12 | AVDD | power_in | Positive analog power supply (2.3 V to 5.5 V relative to AVSS). |
| 13 | DVDD | power_in | Positive digital power supply (2.3 V to 5.5 V relative to DGND). |
| 14 | DRDY | output | Data ready, active low; leave unconnected or tie to DVDD with a weak pull-up resistor if not used. |
| 15 | DOUT/DRDY | output | Serial data output, combined with data ready (active low). |
| 16 | DIN | input | Serial data input. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Shanghai Siproin Microelectronics |
| Package | TSSOP-16 |
| Category | ADC/DAC/Data Conversion |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| AVDD to AVSS (abs max) | -0.3 | 7 | V | 4 | |||
| DVDD to DGND (abs max) | -0.3 | 7 | V | 4 | |||
| AVSS to DGND (abs max) | -2.8 | 0.3 | V | 4 | |||
| Input current | -10 | 10 | mA | Continuous, any pin except power supply pins | 4 | ||
| Junction temperature | TJ | -40 | 150 | ℃ | 4 | ||
| Storage temperature | Tstg | -60 | 150 | ℃ | 4 | ||
| Unipolar analog supply AVDD to AVSS | AVDD | 2.3 | 5.5 | V | Unipolar analog power supply | 4 | |
| AVSS to DGND unipolar | AVSS | -0.1 | 0 | 0.1 | V | Unipolar analog power supply | 4 |
| Bipolar AVDD to DGND | AVDD | 2.3 | 2.5 | 5.5 | V | Bipolar analog power supply | 4 |
| Bipolar AVSS to DGND | AVSS | -2.75 | -2.5 | -2.3 | V | Bipolar analog power supply | 4 |
| Digital supply DVDD to DGND | DVDD | 2.3 | 5.5 | V | 4 | ||
| Differential reference input voltage | Vref | 0.75 | 2.5 | V | Vref = V(REFPx), V(REFNx); max printed as AVDD | 4 | |
| External clock frequency | f(CLK) | 0.5 | 4.096 | 4.5 | MHz | 4 | |
| External clock duty cycle | 40 | 60 | % | 4 | |||
| Operating ambient temperature | TA | -40 | 125 | ℃ | 4 | ||
| Integral nonlinearity | INL | 20 | ppmFSR | Gain=1 to 128, VCM=0.5*AVDD, best fit | 5 | ||
| Input offset voltage, PGA disabled | VIO | -2 | 2 | µV | PGA disabled, gain = 1 to 4, differential inputs | 5 | |
| Input offset voltage, PGA enabled | VIO | -2 | 2 | µV | Gain= 1 to 128, differential inputs | 5 | |
| Offset drift, PGA disabled | 0.1 | 0.3 | µV/℃ | PGA disabled, gain = 1 to 4 | 5 | ||
| Offset drift, -40 to 85℃ | 0.1 | 0.3 | µV/℃ | Gain= 1 to 128, TA= -40℃ to +85℃ | 5 | ||
| Offset drift, gain 1 to 128 | 0.3 | 0.5 | µV/℃ | Gain = 1 to 128 | 5 | ||
| Gain error, PGA disabled | 0.2 | % | PGA disabled, gain = 1 to 4 | 5 | |||
| Gain error, PGA enabled | -0.5 | 0.2 | 0.5 | % | Gain = 1 to 128, TA = 25℃ | 5 | |
| Gain drift, PGA disabled | 5 | ppm/℃ | PGA disabled, gain = 1 to 4 | 5 | |||
| Gain drift, gain 1 to 128 | 5 | 20 | ppm/℃ | Gain = 1 to 128 | 5 | ||
| PSRR AVDD | PSRR | 80 | 105 | dB | AVDD at dc, VCM= 0.5AVDD, gain= 1 | 5 | |
| PSRR DVDD | PSRR | 100 | 115 | dB | DVDD at dc, VCM=0.5AVDD, gain=1 | 5 | |
| Internal reference initial accuracy | 2.048 | V | TA = 25℃ | 5 | |||
| Reference drift -45~125℃ | 5 | 30 | ppm/℃ | -45~125℃ | 5 | ||
| Reference drift -45~85℃ | 4 | 10 | ppm/℃ | -45~85℃ | 5 | ||
| Reference drift 0~85℃ | 3 | 7 | ppm/℃ | 0~85℃ | 5 | ||
| Internal oscillator accuracy | -2 | 1 | 2 | % | Normal mode | 6 | |
| IDAC accuracy | -6 | 1 | 6 | % | All current settings, each IDAC | 6 | |
| IDAC current match | -0.3 | 0.3 | % | Between IDAC | 6 | ||
| Temperature sensor accuracy 0 to 75℃ | -0.5 | 0.5 | ℃ | TA = 0℃ to +75℃ | 6 | ||
| Temperature sensor accuracy -40 to 125℃ | -1 | 1 | ℃ | TA = -40℃ to +125℃ | 6 | ||
| Input leakage, high | IH | -10 | 10 | µA | VIH = 5.5 V | 6 | |
| Input leakage, low | IL | -10 | 10 | µA | VIL = DGND | 7 | |
| Delay CS falling to first SCLK rising | td(CSSC) | 50 | ns | 10 | |||
| Delay final SCLK falling to CS rising | td(SCCS) | 25 | ns | 10 | |||
| CS high pulse duration | tw(CSH) | 50 | ns | 10 | |||
| SCLK period | tc(SC) | 150 | ns | 10 | |||
| SCLK high pulse duration | tw(SCH) | 60 | ns | 10 | |||
| SCLK low pulse duration | tw(SCL) | 60 | ns | 10 | |||
| DIN setup time | tsu(DI) | 50 | ns | DIN valid before SCLK falling edge | 10 | ||
| DIN hold time | th(DI) | 25 | ns | DIN valid after SCLK falling edge | 10 | ||
| Propagation delay CS falling to DOUT driven | tp(CSDO) | 50 | ns | DOUT load = 20 pF // 10 kΩ to DGND | 10 | ||
| Propagation delay SCLK rising to valid DOUT | tp(SCDO) | 0 | 25 | ns | DOUT load = 20 pF // 10 kΩ to DGND | 10 | |
| Propagation delay CS rising to DOUT high-Z | tp(CSDOZ) | 50 | ns | DOUT load = 20 pF // 10 kΩ to DGND | 10 | ||
| Analog supply current, duty-cycle, PGA disabled | IAVDD | 135 | µA | Duty-cycle mode, PGA disabled | 7 | ||
| Analog supply current, normal, PGA disabled | IAVDD | 342 | µA | Normal mode, PGA disabled | 7 | ||
| Analog supply current, turbo, PGA disabled | IAVDD | 402 | µA | Turbo mode, PGA disabled | 7 | ||
| Analog supply current, power-down | IAVDD | 0.05 | µA | Power-down mode | 7 | ||
| Digital supply current, normal | IDVDD | 43 | µA | Normal mode | 7 | ||
| Low-side switch on-resistance | RON | 3 | Ω | 6 |
CAD (KiCad official)
- Symbol:
SSP1220 - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
ssp1220-etched.step/ssp1220-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ssp1220.step/ssp1220.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Shanghai Siproin Microelectronics datasheet (17 pp, sha256
c6d9fffa1a6ba43f, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).