component
SSP1120
Public Made by Adomby adom
Shanghai Siproin Microelectronics Analog To Digital Converters (ADCs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 15d ago |
| viewers | 15d ago |
| package.json | 15d ago |
| page.json | 15d ago |
| README.md | 15d ago |
| ssp1120-etched.glb | 15d ago |
| ssp1120-etched.step | 15d ago |
| ssp1120-hero.glb | 15d ago |
| ssp1120-hero.overlay.json | 15d ago |
| ssp1120.glb | 15d ago |
| ssp1120.kicad_mod | 15d ago |
| ssp1120.kicad_sym | 15d ago |
| ssp1120.lbr | 15d ago |
| ssp1120.step | 15d ago |
SSP1120
Shanghai Siproin Microelectronics · Analog To Digital Converters (ADCs) · TSSOP-16
SSP1120 from Shanghai Siproin Microelectronics, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCLK | input | Serial clock input for the SPI-compatible interface. |
| 2 | CS | input | Chip select, active low; connect to DGND if not used. |
| 3 | CLK | input | External clock source pin (0.5 to 4.5 MHz, 4.096 MHz typ); connect to DGND if not used. |
| 4 | DGND | power_in | Digital ground. |
| 5 | AVSS | power_in | Negative analog power supply. |
| 6 | AIN3/REFN1 | input | Analog input 3 or negative reference input 1, with an internal low-side power switch connected between this pin and AVSS. |
| 7 | AIN2 | input | Analog input 2. |
| 8 | REFN0 | input | Negative reference input 0. |
| 9 | REFP0 | input | Positive reference input 0. |
| 10 | AIN1 | input | Analog input 1. |
| 11 | AIN0/REFP1 | input | Analog input 0 or positive reference input 1. |
| 12 | AVDD | power_in | Positive analog power supply (2.3 V to 5.5 V). |
| 13 | DVDD | power_in | Positive digital power supply (2.3 V to 5.5 V). |
| 14 | DRDY | output | Data ready, active low; leave unconnected or tie to DVDD with a weak pull-up resistor if not used. |
| 15 | DOUT/DRDY | output | Serial data output, combined with active-low data ready. |
| 16 | DIN | input | Serial data input. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Shanghai Siproin Microelectronics |
| Package | TSSOP-16 |
| Category | ADC/DAC/Data Conversion |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog supply voltage AVDD to AVSS | AVDD-AVSS | -0.3 | 7 | V | 4 | ||
| Digital supply voltage DVDD to DGND | DVDD-DGND | -0.3 | 7 | V | 4 | ||
| AVSS to DGND | AVSS-DGND | -2.8 | 0.3 | V | 4 | ||
| Input current | -10 | 10 | mA | Continuous, any pin except power supply pins | 4 | ||
| Junction temperature | TJ | -40 | 150 | ℃ | 4 | ||
| Storage temperature | Tstg | -60 | 150 | ℃ | 4 | ||
| Unipolar analog power supply AVDD to AVSS | AVDD to AVSS | 2.3 | 5.5 | V | 4 | ||
| Digital power supply DVDD to DGND | DVDD to DGND | 2.3 | 5.5 | V | 4 | ||
| Differential reference input voltage | Vref | 0.75 | 2.5 | V | Vref = V(REFPx), V(REFNx) | 4 | |
| External clock frequency | f(CLK) | 0.5 | 4.096 | 4.5 | MHz | 4 | |
| Operating ambient temperature | TA | -40 | 125 | ℃ | 4 | ||
| Gain error | -0.5 | 0.2 | 0.5 | % | Gain = 1 to 128, TA = 25°C | 5 | |
| CMRR at dc | CMRR | 90 | 97 | dB | At dc, gain = 1 | 5 | |
| PSRR AVDD | PSRR | 80 | 105 | dB | AVDD at dc, VCM= 0.5AVDD, gain= 1 | 5 | |
| PSRR DVDD | PSRR | 100 | 115 | dB | DVDD at dc, VCM=0.5AVDD, gain=1 | 5 | |
| Internal oscillator accuracy | -2 | 1 | 2 | % | Normal mode | 6 | |
| IDAC accuracy | -6 | 1 | 6 | % | All current settings, each IDAC | 6 | |
| High-level input voltage | VIH | 0.7 | V | 0.7DVDD min, DVDD max | 6 | ||
| High-level output voltage | VOH | 0.8 | V | IOH = 3 mA; 0.8DVDD | 6 | ||
| Low-level output voltage | VOL | 0.2 | V | IOL = 3 mA; 0.2DVDD | 6 | ||
| Input leakage, high | IH | -10 | 10 | µA | VIH = 5.5 V | 7 | |
| Input leakage, low | IL | -10 | 10 | µA | VIL = DGND | 7 | |
| Delay time, CS falling edge to first SCLK rising edge | td(CSSC) | 50 | ns | 9 | |||
| SCLK period | tc(SC) | 150 | ns | 9 | |||
| Propagation delay SCLK rising edge to valid new DOUT | tp(SCDO) | 0 | 25 | ns | DOUT load = 20 pF // 10 kΩ to DGND | 9 |
CAD (KiCad official)
- Symbol:
SSP1120 - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
ssp1120-etched.step/ssp1120-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ssp1120.step/ssp1120.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Shanghai Siproin Microelectronics datasheet (16 pp, sha256
410bf8fb3687df91, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).