component

SSM3J56MFV

Public Made by Adom

by adom

TOSHIBA MOSFETs, SOT-723. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttransistors-thyristorsssm3j56mfvfactory-2.0.0extractor-text
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Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 24d ago
viewers ssm3j56mfv: viewers · Ray 24d ago
package.json ssm3j56mfv: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
page.json ssm3j56mfv: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
README.md Publish 0.1.0 · Ray 24d ago
ssm3j56mfv-etched.glb ssm3j56mfv: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
ssm3j56mfv-etched.step ssm3j56mfv: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
ssm3j56mfv-hero.glb ssm3j56mfv: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
ssm3j56mfv-hero.overlay.json ssm3j56mfv: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
ssm3j56mfv.glb plain STEP: one free product with face colours (generated model was nested; tscircuit read it white) · Ray 17d ago
ssm3j56mfv.kicad_mod Publish 0.1.0 · Ray 24d ago
ssm3j56mfv.kicad_sym Publish 0.1.0 · Ray 24d ago
ssm3j56mfv.lbr Publish 0.1.0 · Ray 24d ago
ssm3j56mfv.step plain STEP: one free product with face colours (generated model was nested; tscircuit read it white) · Ray 17d ago

SSM3J56MFV

TOSHIBA · MOSFETs · SOT-723

SSM3J56MFV from TOSHIBA, in a SOT-723. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Gate input Gate terminal; gate-source voltage is rated at VGSS ±8 V, and the gate leakage current is ±1 µA max at VGS = ±8 V.
2 Source passive Source terminal of the P-channel MOSFET; the device is rated for a drain-source voltage VDSS of -20 V and a DC drain current of -800 mA (Note 1).
3 Drain passive Drain terminal of the P-channel MOSFET; the device is rated for a drain-source voltage VDSS of -20 V, a DC drain current of -800 mA and a pulse drain current of -1600 mA.

Key specifications

Parameter Value
Manufacturer TOSHIBA
Package SOT-723
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: SSM3J56MFV
  • Footprint: Package_TO_SOT_SMD:SOT-723
  • 3D model: SOT-723, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.5 mm nominal SOT-723 height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: ssm3j56mfv-etched.step / ssm3j56mfv-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ssm3j56mfv.step / ssm3j56mfv.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TOSHIBA datasheet (6 pp, sha256 cb51ad1943530ea7, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF