component
SSM3J15FV
Public Made by Adomby adom
TOSHIBA MOSFETs, SOT-723. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 23d ago |
| viewers | 23d ago |
| package.json | 23d ago |
| page.json | 23d ago |
| README.md | 23d ago |
| ssm3j15fv-etched.glb | 23d ago |
| ssm3j15fv-etched.step | 23d ago |
| ssm3j15fv-hero.glb | 23d ago |
| ssm3j15fv-hero.overlay.json | 23d ago |
| ssm3j15fv.glb | 23d ago |
| ssm3j15fv.kicad_mod | 23d ago |
| ssm3j15fv.kicad_sym | 23d ago |
| ssm3j15fv.lbr | 23d ago |
| ssm3j15fv.step | 23d ago |
SSM3J15FV
TOSHIBA · MOSFETs · SOT-723
SSM3J15FV from TOSHIBA, in a SOT-723. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GATE | input | Gate terminal; gate-source voltage is rated at ±20 V (absolute maximum), and VGS(on) must exceed Vth (−1.1 V to −1.7 V) for normal switching. |
| 2 | SOURCE | passive | Source terminal and reference for the gate-source voltage rating of ±20 V; the datasheet rates the device for drain-source voltage VDSS of −30 V. |
| 3 | DRAIN | passive | Drain terminal; rated at VDSS −30 V, DC drain current ID −100 mA and pulse drain current IDP −200 mA, with power dissipation PD of 150 mW (Ta = 25°C, FR4 board). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | SOT-723 |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Gate leakage current | IGSS | -1 | 1 | μA | VGS = ±16 V, VDS = 0 V | 2 | |
| Drain-Source breakdown voltage | V (BR) DSS | -30 | V | ID = − 0.1 mA, VGS = 0 V | 2 | ||
| Drain cut-off current | IDSS | -1 | μA | VDS = − 30 V, VGS = 0 V | 2 | ||
| Gate threshold voltage | Vth | -1.1 | -1.7 | V | VDS = − 3 V, ID = − 0.1 mA | 2 | |
| Forward transfer admittance | /Yfs/ | 20 | mS | VDS = − 3 V, ID = − 10 mA (Note 2) | 2 | ||
| Drain-Source on-resistance | RDS (ON) | 8 | 12 | Ω | ID = − 10 mA, VGS = − 4 V (Note 2) | 2 | |
| Drain-Source on-resistance | RDS (ON) | 14 | 32 | Ω | ID = − 1 mA, VGS = − 2.5 V (Note 2) | 2 | |
| Drain-Source voltage | VDSS | -30 | V | 1 | |||
| Gate-Source voltage | VGSS | -20 | 20 | V | 1 | ||
| Drain current DC | ID | -100 | mA | 1 | |||
| Drain current pulse | IDP | -200 | mA | 1 | |||
| Power dissipation | PD | 150 | mW | Note 1: Mounted on FR4 board (25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 0.585 mm2) | 1 | ||
| Channel temperature | Tch | 150 | °C | 1 | |||
| Storage temperature range | Tstg | -55 | 150 | °C | 1 |
CAD (KiCad official)
- Symbol:
SSM3J15FV - Footprint:
Package_TO_SOT_SMD:SOT-723 - 3D model: SOT-723, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.5 mm nominal SOT-723 height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
ssm3j15fv-etched.step/ssm3j15fv-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ssm3j15fv.step/ssm3j15fv.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (5 pp, sha256
ac4dd51b4b5e0baf, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).