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SSM14N956L

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TOSHIBA MOSFETs, DFN-14(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SSM14N956L

TOSHIBA · MOSFETs · DFN-14(3x3)

SSM14N956L from TOSHIBA, in a DFN-14(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Gate 1 input Gate terminal of MOSFET 1, with a built-in protection diode and series resistor; VGSS rating is ±8 V.
2 Source 1 passive Source 1 terminal of the common-drain dual MOSFET, tied internally with pins 3-7.
3 Source 1 passive Source 1 terminal of the common-drain dual MOSFET, tied internally with pins 2 and 4-7.
4 Source 1 passive Source 1 terminal of the common-drain dual MOSFET, tied internally with pins 2, 3 and 5-7.
5 Source 1 passive Source 1 terminal of the common-drain dual MOSFET, tied internally with pins 2-4, 6 and 7.
6 Source 1 passive Source 1 terminal of the common-drain dual MOSFET, tied internally with pins 2-5 and 7.
7 Source 1 passive Source 1 terminal of the common-drain dual MOSFET, tied internally with pins 2-6.
8 Gate 2 input Gate terminal of MOSFET 2, with a built-in protection diode and series resistor; VGSS rating is ±8 V.
9 Source 2 passive Source 2 terminal of the common-drain dual MOSFET, tied internally with pins 10-14.
10 Source 2 passive Source 2 terminal of the common-drain dual MOSFET, tied internally with pins 9 and 11-14.
11 Source 2 passive Source 2 terminal of the common-drain dual MOSFET, tied internally with pins 9, 10 and 12-14.
12 Source 2 passive Source 2 terminal of the common-drain dual MOSFET, tied internally with pins 9-11, 13 and 14.
13 Source 2 passive Source 2 terminal of the common-drain dual MOSFET, tied internally with pins 9-12 and 14.
14 Source 2 passive Source 2 terminal of the common-drain dual MOSFET, tied internally with pins 9-13.
15 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer TOSHIBA
Package DFN-14(3x3)
Category Transistors/Thyristors
Pins 15

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Source-source voltage VSSS 12 V Ta = 25°C 2
Gate-source voltage VGSS -8 8 V Ta = 25°C 2
Source current (DC) IS 20 A Ta = 25°C 2
Source current (pulsed) ISP 200 A Pulse width ≤ 10 µs, Duty ≤ 1 % 2
Power dissipation PD 1.33 W Device mounted on 25 mm × 27.5 mm FR4 board, 407 mm2 Cu pad 2
Power dissipation (t ≤ 10 s) PD 2.44 W t ≤ 10 s; device mounted on 25 mm × 27.5 mm FR4 board, 407 mm2 Cu pad 2
Channel temperature Tch 150 °C 2
Storage temperature Tstg -55 150 °C 2
Gate-source leakage current IGSS -1 1 µA VSS = 0 V, VGS = ±8 V 3
Source-source current (zero-gate voltage) ISSS 1 µA VSS = 12 V, VGS = 0 V 3
Source-source breakdown voltage V(BR)SSS 12 V IS = 1 mA, VGS = 0 V 3
Gate threshold voltage Vth 0.35 0.9 1.4 V VSS = 6 V, IS = 1.57 mA 3
Source-source on-resistance RSS(ON) 0.7 1 1.35 mΩ IS = 10 A, VGS = 4.5 V 3
Source-source on-resistance RSS(ON) 0.75 1.1 1.5 mΩ IS = 10 A, VGS = 3.8 V 3
Source-source on-resistance RSS(ON) 0.8 1.25 2.15 mΩ IS = 10 A, VGS = 3.1 V 3
Source-source on-resistance RSS(ON) 0.9 1.6 3.2 mΩ IS = 10 A, VGS = 2.5 V 3
Body diode forward voltage VF(S-S) 0.7 1.2 V IF = 10 A, VGS = 0 V 3
Turn-on delay time td(on) 1 µs VDD = 6 V, IS = 10.0 A, VGS = 0 to 4.0 V, RG = 50 Ω, RL = 0.6 Ω 3
Rise time tr 1.3 µs VDD = 6 V, IS = 10.0 A, VGS = 0 to 4.0 V, RG = 50 Ω, RL = 0.6 Ω 3
Turn-off delay time td(off) 3.8 µs VDD = 6 V, IS = 10.0 A, VGS = 0 to 4.0 V, RG = 50 Ω, RL = 0.6 Ω 3
Fall time tf 2.1 µs VDD = 6 V, IS = 10.0 A, VGS = 0 to 4.0 V, RG = 50 Ω, RL = 0.6 Ω 3
Total gate charge Qg 76 nC VDD = 6 V, IS = 20.0 A, VGS = 4.0 V 3
Gate-source charge 1 Qgs1 17 nC VDD = 6 V, IS = 20.0 A 3
Gate-drain charge Qgd 17 nC VDD = 6 V, IS = 20.0 A 3

CAD (KiCad official)

  • Symbol: SSM14N956L
  • Footprint: Package_DFN_QFN:DFN-14-1EP_3x3mm_P0.4mm_EP1.78x2.35mm
  • 3D model: DFN-14(3x3) (KiCad packages3D, STEP)
  • 3D model files: ssm14n956l-etched.step / ssm14n956l-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ssm14n956l.step / ssm14n956l.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TOSHIBA datasheet (8 pp, sha256 4b0047dc5f5d4f6c, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF