component

SS6226-SO-TP

Public Made by Adom

by adom

LEADPOWER Motor Driver ICs, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower supply chipss6226-so-tpfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4d ago
viewers ss6226-so-tp: viewers · Ray 4d ago
package.json Publish 0.1.0 · Ray 4d ago
page.json Set visibility: public · Ray 4d ago
README.md Publish 0.1.0 · Ray 4d ago
ss6226-so-tp-etched.glb Publish 0.1.0 · Ray 4d ago
ss6226-so-tp-etched.step ss6226-so-tp: factory component page (tier=lcsc) · Ray 4d ago
ss6226-so-tp-hero.glb ss6226-so-tp: hero GLB from the etched model (keeps the MPN mark) · Ray 4d ago
ss6226-so-tp-hero.overlay.json Publish 0.1.0 · Ray 4d ago
ss6226-so-tp.glb Publish 0.1.0 · Ray 4d ago
ss6226-so-tp.kicad_mod Publish 0.1.0 · Ray 4d ago
ss6226-so-tp.kicad_sym Publish 0.1.0 · Ray 4d ago
ss6226-so-tp.lbr Publish 0.1.0 · Ray 4d ago
ss6226-so-tp.step Publish 0.1.0 · Ray 4d ago

SS6226-SO-TP

LEADPOWER · Motor Driver ICs · SOP-16

SS6226-SO-TP from LEADPOWER, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connection (undefined function per datasheet).
2 INA1 input Channel A forward-rotation input; logic high VINH min 2.0 V, low VINL max 0.8 V, input range 0 to VDD.
3 INA2 input Channel A reverse-rotation input; logic high VINH min 2.0 V, low VINL max 0.8 V, input range 0 to VDD.
4 VDD1 power_in Power supply terminal, operating range 2.4 V to 7.2 V; decoupling capacitor must be placed as close to the chip as possible.
5 NC unconnected No connection (undefined function per datasheet).
6 INB1 input Channel B forward-rotation input; logic high VINH min 2.0 V, low VINL max 0.8 V, input range 0 to VDD.
7 INB2 input Channel B reverse-rotation input; logic high VINH min 2.0 V, low VINL max 0.8 V, input range 0 to VDD.
8 VDD2 power_in Power supply terminal, operating range 2.4 V to 7.2 V; decoupling capacitor must be placed as close to the chip as possible.
9 OUTB2 output Channel B reverse-rotation output; do not short directly to ground or supply, 1.4 A max continuous output current.
10 AGND2 power_in Analog ground terminal.
11 PGND2 power_in Power ground terminal.
12 OUTB1 output Channel B forward-rotation output; do not short directly to ground or supply, 1.4 A max continuous output current.
13 OUTA2 output Channel A reverse-rotation output; do not short directly to ground or supply, 1.4 A max continuous output current.
14 AGND1 power_in Analog ground terminal.
15 PGND1 power_in Power ground terminal.
16 OUTA1 output Channel A forward-rotation output; do not short directly to ground or supply, 1.4 A max continuous output current.

Key specifications

Parameter Value
Manufacturer LEADPOWER
Package SOP-16
Category Power Supply Chip
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.3 7.2 V 4
Input voltage INx1, INx2 -0.3 V max is VDD 4
Operating temperature TOP -30 85 °C 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -55 150 °C 4
Continuous output current Icon 0 1.4 A depends on heat dissipation 4
Power dissipation Pd 0.96 W 4
Supply voltage VDD 2.4 7.2 V 5
Input voltage INx1, INx2 0 V max is VDD 5
Standby current IDDST 0 20 uA INx1=INx2=L 5
Operating current IDD 0.2 1 mA INx1=INx2=H or INx1=H, INx2=L or INx1=L, INx2=H 5
High-level input voltage VINH 2 V 5
Low-level input voltage VINL 0.8 V 5
High-level input current IINH 0 uA 5
Low-level input current IINL 3.75 20 uA 5
Pull-down resistance RIN 1.25 MΩ 5
Output on-resistance RON 0.6 0.7 Ω IOUT=0.8A (PMOS+NMOS) 5

CAD (KiCad official)

  • Symbol: SS6226-SO-TP
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: ss6226-so-tp-etched.step / ss6226-so-tp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ss6226-so-tp.step / ss6226-so-tp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LEADPOWER datasheet (6 pp, sha256 9ca42b84652da8dc, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF