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Initial commit: component/ss4127

Ray ·297804eba2 ·29d ago
2 files changed +84
README.mdadded+50
@@ -0,0 +1,50 @@+# SS4127++**orisilicon** · Leakage Protection ICs · SOP-8++SS4127 from orisilicon, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | IN1 | input | Op-amp input 1 (leakage-sense differential input, connected to current-transformer secondary). Trip threshold |IN1 - IN2| = 4.95 mV typical. |+| 2 | IN2 | input | Op-amp input 2 (leakage-sense differential input, connected to current-transformer secondary). |+| 3 | GND | power_in | Device ground reference. |+| 4 | OA | output | Op-amp / filter output and reverse-time delay adjustment pin. External capacitor (C_OA, e.g. 33 nF) forms the integrator that generates the inverse-time trip curve; internal threshold is 1.5 V. |+| 5 | DLY | output | Fixed-delay control pin. An external capacitor C_D to GND sets the trip delay via T_D = C_D × V_REF / I_D (V_REF = 1.5 V, I_D ≈ 3 µA). E.g. 0.8 µF → ~0.4 s; 3.42 µF → ~1.71 s. |+| 6 | OSHV | output | High-voltage MOSFET trip driver output. Drives external high-voltage MOS gate; typical output voltage ~10 V (with VS=12V), delivers 3 pulses of 30 ms with 100 ms period on trip. |+| 7 | OSLV | output | Low-voltage SCR (thyristor) trigger output. Typical output ~5 V (with VS=12V), source current up to ~750 µA (OS=0.8 V); provides 3 pulses of 30 ms with 100 ms period on trip. |+| 8 | VS | power_in | Supply pin. Internal clamp/regulator: V_S1 ≈ 12 V typical (I_S = 1 mA). Absolute max VS to GND: -0.3 V to +24 V. Typical quiescent current 180 µA. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | orisilicon |+| Package | SOP-8 |+| Category | Power Management (PMIC) |+| Pins | 8 |++## Ordering variants++Same part, different packaging or reel option.++- `SS4127`++## CAD (KiCad official)++- Symbol: `SS4127`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOP-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [orisilicon datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603322322502250496) (16 pp, sha256 `77533e6513c282e4`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ss4127-datasheet.pdf)
page.jsonadded+34
@@ -0,0 +1,34 @@+{+  "slug": "ss4127",+  "version": "0.1.0",+  "type": "component",+  "description": "orisilicon Leakage Protection ICs, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "power management (pmic)",+    "ss4127"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "ss4127.kicad_sym",+    "ss4127.kicad_mod",+    "ss4127.glb",+    "ss4127.step",+    "ss4127.lbr",+    "docs/hero.png",+    "docs/ss4127-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file