component
SS15-E3
Public Made by Adomby adom
Vishay Intertech Schottky Barrier Diodes (SBD), DO-214AC. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownSS15-E3
Vishay Intertech · Schottky Barrier Diodes (SBD) · DO-214AC
SS15-E3 from Vishay Intertech, in a DO-214AC. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Cathode | passive | Cathode terminal, identified by the color band on the SMA (DO-214AC) package; VRRM of 50 V for SS15 with IF(AV) 1.0 A. |
| 2 | Anode | passive | Anode terminal at the end opposite the cathode band of the SMA (DO-214AC) single Schottky rectifier. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | DO-214AC |
| Category | Diodes |
| Pins | 2 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum repetitive peak reverse voltage | VRRM | 50 | V | TA = 25 °C | 1 | ||
| Maximum RMS voltage | VRMS | 35 | V | TA = 25 °C | 1 | ||
| Maximum DC blocking voltage | VDC | 50 | V | TA = 25 °C | 1 | ||
| Maximum average forward rectified current | IF(AV) | 1 | A | at TL (fig. 1) | 1 | ||
| Peak forward surge current | IFSM | 40 | A | 8.3 ms single half sine-wave superimposed on rated load | 1 | ||
| Voltage rate of change | dV/dt | 10000 | V/μs | rated VR | 1 | ||
| Operating junction temperature range | TJ | -65 | 150 | °C | 1 | ||
| Storage temperature range | TSTG | -65 | 150 | °C | 1 | ||
| Maximum instantaneous forward voltage | VF | 0.75 | V | 1.0 A | 2 | ||
| Maximum DC reverse current at rated DC blocking voltage | IR | 0.2 | mA | TA = 25 °C | 2 | ||
| Maximum DC reverse current at rated DC blocking voltage | IR | 5 | mA | TA = 100 °C | 2 | ||
| Typical thermal resistance junction to ambient | RθJA | 88 | °C/W | PCB mounted with 0.2" x 0.2" (5.0 mm x 5.0 mm) copper pad areas | 2 | ||
| Typical thermal resistance junction to lead | RθJL | 28 | °C/W | PCB mounted with 0.2" x 0.2" (5.0 mm x 5.0 mm) copper pad areas | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | Terminals: matte tin plated leads, solderable per J-STD-002 and JESD 22-B102 | 1 |
CAD (KiCad official)
- Symbol:
SS15-E3 - Footprint:
Diode_SMD:D_SMA - 3D model: DO-214AC (KiCad packages3D, STEP)
- 3D model files:
ss15-e3-etched.step/ss15-e3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ss15-e3.step/ss15-e3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (5 pp, sha256
e11eab7dfacb885a, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).