component
SS12-E3
Public Made by Adomby adom
Vishay Intertech Schottky Barrier Diodes (SBD), DO-214AC. Unpolarised two-terminal part: the datasheet prints no pin numbers, so pins 1 and 2 follow the library convention, KiCad symbol/footprint/3D.
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SS12-E3
Vishay Intertech · Schottky Barrier Diodes (SBD) · DO-214AC
SS12-E3 from Vishay Intertech, in a DO-214AC. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | K | passive | Cathode: the banded/marked end per the datasheet; pad 1 of the KiCad diode footprint. |
| 2 | A | passive | Anode. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | DO-214AC |
| Category | Diodes |
| Pins | 2 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum instantaneous forward voltage | VF | 0.5 | V | 1.0 A, pulse test 300 µs pulse width, 1% duty cycle (SS12 column) | 2 | ||
| Maximum DC reverse current at rated DC blocking voltage, TA = 25 °C | IR | 0.2 | mA | TA = 25 °C, at rated DC blocking voltage, pulse test pulse width ≤ 40 ms | 2 | ||
| Maximum DC reverse current at rated DC blocking voltage, TA = 100 °C | IR | 6 | mA | TA = 100 °C, at rated DC blocking voltage, pulse test pulse width ≤ 40 ms | 2 | ||
| Maximum repetitive peak reverse voltage | VRRM | 20 | V | 1 | |||
| Maximum RMS voltage | VRMS | 14 | V | 1 | |||
| Maximum DC blocking voltage | VDC | 20 | V | 1 | |||
| Maximum average forward rectified current | IF(AV) | 1 | A | at TL (fig. 1) | 1 | ||
| Peak forward surge current | IFSM | 40 | A | 8.3 ms single half sine-wave superimposed on rated load | 1 | ||
| Voltage rate of change (rated VR) | dV/dt | 10000 | V/μs | rated VR | 1 | ||
| Operating junction temperature range | TJ | -65 | 150 | °C | 1 | ||
| Storage temperature range | TSTG | -65 | 150 | °C | 1 | ||
| Typical thermal resistance, junction to ambient | RθJA | 88 | °C/W | PCB mounted with 0.2" x 0.2" (5.0 mm x 5.0 mm) copper pad areas | 2 | ||
| Typical thermal resistance, junction to lead | RθJL | 28 | °C/W | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | Terminals: matte tin plated leads, solderable per J-STD-002 and JESD 22-B102 | 1 |
CAD (KiCad official)
- Symbol:
SS12-E3 - Footprint:
Diode_SMD:D_SMA - 3D model: DO-214AC (KiCad packages3D, STEP)
- 3D model files:
ss12-e3-etched.step/ss12-e3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ss12-e3.step/ss12-e3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (4 pp, sha256
84f451af1ad4a0cb, retrieved 2026-10-21, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins, primarycathode-band convention(convention), consensusoff(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SS12-E3
**Vishay Intertech** · Schottky Barrier Diodes (SBD) · DO-214AC
SS12-E3 from Vishay Intertech, in a DO-214AC. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | K | passive | Cathode: the banded/marked end per the datasheet; pad 1 of the KiCad diode footprint. |
| 2 | A | passive | Anode. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | DO-214AC |
| Category | Diodes |
| Pins | 2 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum instantaneous forward voltage | VF | | | 0.5 | V | 1.0 A, pulse test 300 µs pulse width, 1% duty cycle (SS12 column) | 2 |
| Maximum DC reverse current at rated DC blocking voltage, TA = 25 °C | IR | | | 0.2 | mA | TA = 25 °C, at rated DC blocking voltage, pulse test pulse width ≤ 40 ms | 2 |
| Maximum DC reverse current at rated DC blocking voltage, TA = 100 °C | IR | | | 6 | mA | TA = 100 °C, at rated DC blocking voltage, pulse test pulse width ≤ 40 ms | 2 |
| Maximum repetitive peak reverse voltage | VRRM | | | 20 | V | | 1 |
| Maximum RMS voltage | VRMS | | | 14 | V | | 1 |
| Maximum DC blocking voltage | VDC | | | 20 | V | | 1 |
| Maximum average forward rectified current | IF(AV) | | | 1 | A | at TL (fig. 1) | 1 |
| Peak forward surge current | IFSM | | | 40 | A | 8.3 ms single half sine-wave superimposed on rated load | 1 |
| Voltage rate of change (rated VR) | dV/dt | | | 10000 | V/μs | rated VR | 1 |
| Operating junction temperature range | TJ | -65 | | 150 | °C | | 1 |
| Storage temperature range | TSTG | -65 | | 150 | °C | | 1 |
| Typical thermal resistance, junction to ambient | RθJA | | 88 | | °C/W | PCB mounted with 0.2" x 0.2" (5.0 mm x 5.0 mm) copper pad areas | 2 |
| Typical thermal resistance, junction to lead | RθJL | | 28 | | °C/W | | 2 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | Terminals: matte tin plated leads, solderable per J-STD-002 and JESD 22-B102 | 1 |
## CAD (KiCad official)
- Symbol: `SS12-E3`
- Footprint: `Diode_SMD:D_SMA`
- 3D model: DO-214AC (KiCad packages3D, STEP)
- 3D model files: `ss12-e3-etched.step` / `ss12-e3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ss12-e3.step` / `ss12-e3.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Vishay Intertech datasheet](docs/ss12-e3-datasheet.pdf) (4 pp, sha256 `84f451af1ad4a0cb`, retrieved 2026-10-21, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins`, primary `cathode-band convention` (convention), consensus `off` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ss12-e3-datasheet.pdf)