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SRC4382IPFBR

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Texas Instruments Audio Interface ICs, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SRC4382IPFBR

Texas Instruments · Audio Interface ICs · TQFP-48(7x7)

SRC4382IPFBR from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RX1+ input Line Receiver 1 Noninverting Input for differential AES3 digital audio interface with 150 to 200 mV differential sensitivity.
2 RX1- input Line Receiver 1 Inverting Input for differential AES3 digital audio interface with 150 to 200 mV differential sensitivity.
3 RX2+ input Line Receiver 2 Noninverting Input for differential AES3 digital audio interface with 150 to 200 mV differential sensitivity.
4 RX2- input Line Receiver 2 Inverting Input for differential AES3 digital audio interface with 150 to 200 mV differential sensitivity.
5 RX3+ input Line Receiver 3 Noninverting Input for differential AES3 digital audio interface with 150 to 200 mV differential sensitivity.
6 RX3- input Line Receiver 3 Inverting Input for differential AES3 digital audio interface with 150 to 200 mV differential sensitivity.
7 RX4+ input Line Receiver 4 Noninverting Input for differential AES3 digital audio interface with 150 to 200 mV differential sensitivity.
8 RX4- input Line Receiver 4 Inverting Input for differential AES3 digital audio interface with 150 to 200 mV differential sensitivity.
9 VCC power_in Digital Interface Receiver (DIR) Comparator and Phase-Locked Loop Power Supply, +3.3V nominal.
10 AGND power_in Analog and DIR Comparator Ground; connect to substrate ground BGND (pin 44) for best noise performance.
11 LOCK output DIR PLL Lock Flag active-low output indicating AES3 decoder and PLL2 locked condition.
12 RXCKO tri_state DIR Recovered Master Clock tri-state output, 3.5 to 27.7 MHz, can be disabled to high-impedance state.
13 RXCKI input DIR Reference Clock Input, 3.5 to 27.7 MHz, used as PLL1 reference with 45 to 55% duty cycle.
14 MUTE input SRC Output Mute active-high input; combined with MUTE control bit via OR function to mute SRC output.
15 RDY output SRC Ready Flag active-low output indicating completion of rate estimation process.
16 DGND1 power_in Digital Core Ground for VDD18 power supply.
17 VDD18 power_in Digital Core Supply, +1.8V nominal (range +1.65V to +1.95V) for internal logic.
18 CPM input Control Port Mode selection; 0 = SPI mode, 1 = I2C mode to select host interface protocol.
19 CS or A0 input Chip Select active-low for SPI mode; Programmable Slave Address bit A0 for I2C mode.
20 CCLK or SCL input Serial Clock for SPI mode or I2C bus clock; supports up to 40 MHz SPI or 100/400 kHz I2C.
21 CDIN or A1 input SPI Serial Data Input for SPI mode; Programmable Slave Address bit A1 for I2C mode.
22 CDOUT or SDA tri_state SPI Serial Data Output tri-state for SPI mode; I2C Serial Data open-drain bidirectional for I2C mode.
23 INT tri_state Interrupt Flag open-drain active-low output; requires external pull-up resistor to VIO supply.
24 RST input Reset active-low input with minimum 500 ns pulse width; initializes all registers to default state.
25 MCLK input Master Clock Input, 1 to 27.7 MHz with 45 to 55% duty cycle for audio serial ports and DIT.
26 GPO1 output General-Purpose Digital Output 1 with programmable function assignment via control registers.
27 GPO2 output General-Purpose Digital Output 2 with programmable function assignment via control registers.
28 GPO3 output General-Purpose Digital Output 3 with programmable function assignment via control registers.
29 GPO4 output General-Purpose Digital Output 4 with programmable function assignment via control registers.
30 DGND2 power_in Digital Ground for DIR Line Receiver bias and DIT Line Driver circuits.
31 TX- output DIT Line Driver Inverting Output for differential AES3 transmission with 5.4 VPP across TX+ and TX-.
32 TX+ output DIT Line Driver Noninverting Output for differential AES3 transmission with 5.4 VPP across TX+ and TX-.
33 VDD33 power_in DIR Line Receiver Bias and DIT Line Driver Supply, +3.3V nominal (range +3.0V to +3.6V).
34 AESOUT output DIT Buffered AES3-Encoded Data CMOS logic-level output compatible with optical transmitters.
35 BLS bidirectional DIT Block Start Clock, programmable as input or output to control AES3 block start condition.
36 SYNC output DIT Internal Sync Clock output aligned with AES3 subframe start for timing reference.
37 BCKA bidirectional Audio Serial Port A Bit Clock, input in slave mode or 64× LRCK output in master mode operation.
38 LRCKA bidirectional Audio Serial Port A Left/Right Clock, input in slave mode or output at sampling rate in master mode.
39 SDINA input Audio Serial Port A Data Input supporting 24-bit audio data with setup and hold times of 10 ns.
40 SDOUTA output Audio Serial Port A Data Output supporting 24-bit audio data with 10 ns propagation delay.
41 NC unconnected No Internal Signal Connection; pad internally bonded to ESD protection network.
42 VIO power_in Logic I/O Supply for digital interface, range +1.65V to +3.6V for flexible low-voltage compatibility.
43 DGND3 power_in Logic I/O Ground for VIO supply.
44 BGND power_in Substrate Ground; must be connected to AGND (pin 10) via PCB trace for noise reduction.
45 SDOUTB output Audio Serial Port B Data Output supporting 24-bit audio data with 10 ns propagation delay.
46 SDINB input Audio Serial Port B Data Input supporting 24-bit audio data with setup and hold times of 10 ns.
47 LRCKB bidirectional Audio Serial Port B Left/Right Clock, input in slave mode or output at sampling rate in master mode.
48 BCKB bidirectional Audio Serial Port B Bit Clock, input in slave mode or 64× LRCK output in master mode operation.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-48(7x7)
Category Interface
Pins 48

CAD (KiCad official)

  • Symbol: SRC4382IPFBR
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: src4382ipfbr-etched.step / src4382ipfbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); src4382ipfbr.step / src4382ipfbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (85 pp, sha256 936226e5e0055ca5, retrieved 2026-09-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF