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SRC4184IPAGR

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Texas Instruments Audio Interface ICs, TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SRC4184IPAGR

Texas Instruments · Audio Interface ICs · TQFP-64(10x10)

SRC4184IPAGR from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IFMTA0 input SRC A audio input data format selection bit 0 (3-bit selector, disabled in software mode).
2 IFMTA1 input SRC A audio input data format selection bit 1 (3-bit selector, disabled in software mode).
3 IFMTA2 input SRC A audio input data format selection bit 2 (3-bit selector, disabled in software mode).
4 OFMTA0 input SRC A audio output data format selection bit 0 (disabled in software mode).
5 OFMTA1 input SRC A audio output data format selection bit 1 (disabled in software mode).
6 OWLA0 input SRC A audio output word length selection bit 0 for 16-, 18-, 20-, or 24-bit data (disabled in software mode).
7 OWLA1 input SRC A audio output word length selection bit 1 for 16-, 18-, 20-, or 24-bit data (disabled in software mode).
8 BYPA input SRC A bypass mode control; active high routes input port data directly to output port (disabled in software mode).
9 LGRPA0 input SRC A low group delay mode selection bit 0 with four options (disabled in software mode).
10 LGRPA1 input SRC A low group delay mode selection bit 1 with four options (disabled in software mode).
11 DDNA input SRC A direct downsampling mode control; active high enables direct downsampling for decimation filter (disabled in software mode).
12 DEMA0 input SRC A digital de-emphasis filter mode selection bit 0 for 32kHz, 44.1kHz, or 48kHz (disabled in software mode).
13 DEMA1 input SRC A digital de-emphasis filter mode selection bit 1 for 32kHz, 44.1kHz, or 48kHz (disabled in software mode).
14 MODEA0 input SRC A serial port mode selection bit 0 for I2S, Left-Justified, Right-Justified, or TDM formats (disabled in software mode).
15 MODEA1 input SRC A serial port mode selection bit 1 for I2S, Left-Justified, Right-Justified, or TDM formats (disabled in software mode).
16 MODEA2 input SRC A serial port mode selection bit 2 for I2S, Left-Justified, Right-Justified, or TDM formats (disabled in software mode).
17 RATIOA output SRC A ratio flag output indicating input-to-output sampling ratio change or readback capability in software mode.
18 RDYA output SRC A ready flag output, active low indicating device ready status.
19 MUTEA input SRC A output soft mute control; active high mutes the SRC A output.
20 RCKIA input SRC A reference clock input for asynchronous sample rate conversion timing.
21 RST input Active low reset and power-down control input for the entire device.
22 H/S input Control mode selection input: logic 0 selects software mode via SPI, logic 1 selects hardware mode via dedicated control pins.
23 DGND power_in Digital ground reference.
24 VDD33 power_in Core supply voltage +3.3V, required when REGEN is high; leave unconnected when REGEN is low.
25 VDD33 power_in Core supply voltage +3.3V, required when REGEN is high; leave unconnected when REGEN is low.
26 REGEN input Voltage regulator enable control input; active high enables on-chip +1.8V linear voltage regulator when using +3.3V core supply.
27 VDD18 power_in Core supply voltage +1.8V, required when REGEN is low; leave unconnected when REGEN is high.
28 VDD18 power_in Core supply voltage +1.8V, required when REGEN is low; leave unconnected when REGEN is high.
29 RCKIB input SRC B reference clock input for asynchronous sample rate conversion timing.
30 MUTEB input SRC B output soft mute control; active high mutes the SRC B output.
31 RDYB output SRC B ready flag output, active low indicating device ready status.
32 RATIOB output SRC B ratio flag output indicating input-to-output sampling ratio change or readback capability in software mode.
33 MODEB2/CDIN input SRC B serial port mode selection bit 2 (hardware mode, disabled in software mode) or SPI port serial data input (software mode only).
34 MODEB1/CCLK input SRC B serial port mode selection bit 1 (hardware mode, disabled in software mode) or SPI port data clock (software mode only).
35 MODEB0/CS input SRC B serial port mode selection bit 0 (hardware mode, disabled in software mode) or active low SPI port chip select (software mode only).
36 DEMB1/CDOUT tri_state SRC B digital de-emphasis filter mode bit 1 (hardware mode, disabled in software mode) or SPI port serial data output in high-impedance tri-state (software mode only).
37 DEMB0 input SRC B digital de-emphasis filter mode selection bit 0 for 32kHz, 44.1kHz, or 48kHz (disabled in software mode).
38 DDNB input SRC B direct downsampling mode control; active high enables direct downsampling for decimation filter (disabled in software mode).
39 LGRPB1 input SRC B low group delay mode selection bit 1 with four options (disabled in software mode).
40 LGRPB0 input SRC B low group delay mode selection bit 0 with four options (disabled in software mode).
41 BYPB input SRC B bypass mode control; active high routes input port data directly to output port (disabled in software mode).
42 OWLB1 input SRC B audio output word length selection bit 1 for 16-, 18-, 20-, or 24-bit data (disabled in software mode).
43 OWLB0 input SRC B audio output word length selection bit 0 for 16-, 18-, 20-, or 24-bit data (disabled in software mode).
44 OFMTB1 input SRC B audio output data format selection bit 1 (disabled in software mode).
45 OFMTB0 input SRC B audio output data format selection bit 0 (disabled in software mode).
46 IFMTB2 input SRC B audio input data format selection bit 2 (3-bit selector, disabled in software mode).
47 IFMTB1 input SRC B audio input data format selection bit 1 (3-bit selector, disabled in software mode).
48 IFMTB0 input SRC B audio input data format selection bit 0 (3-bit selector, disabled in software mode).
49 SDOUTB output SRC B audio output serial data supporting 16-, 18-, 20-, or 24-bit formats with dithering from 28-bit internal path.
50 BCKOB bidirectional SRC B audio output bit clock with master or slave mode operation capability.
51 LRCKOB bidirectional SRC B audio output left/right or word clock with master or slave mode operation capability.
52 TDMIB input SRC B TDM input data for time-division multiplexed format supporting daisy-chaining of up to four devices.
53 BCKIB bidirectional SRC B audio input bit clock with master or slave mode operation capability.
54 LRCKIB bidirectional SRC B audio input left/right or word clock with master or slave mode operation capability.
55 SDINB input SRC B audio input serial data supporting I2S, Left-Justified, Right-Justified, and TDM data formats.
56 VIO power_in Digital I/O supply voltage ranging from +1.65V to +3.6V for all digital input/output pins.
57 DGND power_in Digital ground reference.
58 SDINA input SRC A audio input serial data supporting I2S, Left-Justified, Right-Justified, and TDM data formats.
59 LRCKIA bidirectional SRC A audio input left/right or word clock with master or slave mode operation capability.
60 BCKIA bidirectional SRC A audio input bit clock with master or slave mode operation capability.
61 TDMIA input SRC A TDM input data for time-division multiplexed format supporting daisy-chaining of up to four devices.
62 LRCKOA bidirectional SRC A audio output left/right or word clock with master or slave mode operation capability.
63 BCKOA bidirectional SRC A audio output bit clock with master or slave mode operation capability.
64 SDOUTA output SRC A audio output serial data supporting 16-, 18-, 20-, or 24-bit formats with dithering from 28-bit internal path.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-64(10x10)
Category Interface
Pins 64

CAD (KiCad official)

  • Symbol: SRC4184IPAGR
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: src4184ipagr-etched.step / src4184ipagr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); src4184ipagr.step / src4184ipagr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 f08b50b8a7f99424, retrieved 2026-10-01, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF