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SRC0CS25D

STMicroelectronics · Supervisor And Reset ICs · DFN-12(2x3)

SRC0CS25D from STMicroelectronics, in a DFN-12(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in VCC is the power supply input, monitored during startup and normal operation, and should be decoupled to ground with a 0.1 µF capacitor placed as close to the device as possible.
2 SR input Smart Reset button input with a factory-trimmed voltage detector and ±8 kV HBM ESD protection; it is usually connected to GND through a push-button, must not be grounded permanently, and is monitored for a falling edge after power-up.
3 VREF power_out Precise 1.5 V voltage reference specified with 1% accuracy, which requires a mandatory capacitor on the output even when unused (1 µF recommended).
4 PSHOLD input Input with a factory-trimmed voltage detector used to confirm power-up or initiate shutdown, with an internal pull-down during startup, where forcing it low during normal operation deasserts the enable output.
5 CSRD passive Smart Reset delay time input where a capacitor to ground sets the additional delay tSRD, and the pin should be left open if no capacitor is used.
6 PB input Power ON push-button input with a factory-trimmed voltage detector and ±8 kV HBM ESD protection, which must be switched to GND and has an internal 100 kΩ pull-up resistor.
7 VCCLO output High threshold (VTH+) detection output that is active-low and open drain by default, goes low when VCC is below VTH+ or during undervoltage, and requires a pull-up resistor (10 kΩ is sufficient in most applications).
8 PBOUT output Status output of the PB input that is active-low and open drain by default, stays low for at least tINT_Min after a valid press, ignores PB during undervoltage, and requires a pull-up resistor (10 kΩ is sufficient in most applications).
9 EN output Enable output asserted high after a valid turn-on is detected and confirmed, released low if the push-button is released before PSHOLD goes high, PSHOLD is driven low in normal operation, or an undervoltage or long push condition occurs as applicable; it is push-pull by default.
10 RST output Active-low open drain reset output that pulls low for tREC (240 ms min. per the product selector) during startup and, for the option asserting reset after long push, after a long push; it requires a pull-up resistor (10 kΩ is sufficient in most applications).
11 INT output Active-low open drain interrupt output driven low for at least tINT_Min when VCC falls below VTH- or when the push-button is held for tDEBOUNCE or more during normal operation, and it requires a pull-up resistor (10 kΩ is sufficient in most applications).
12 GND power_in Ground reference pin for the device.
13 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package DFN-12(2x3)
Category Power Management (PMIC)
Pins 13

CAD (KiCad official)

  • Symbol: SRC0CS25D
  • Footprint: Package_DFN_QFN:DFN-12-1EP_2x3mm_P0.45mm_EP0.64x2.4mm
  • 3D model: DFN-12(2x3) (KiCad packages3D, STEP)
  • 3D model files: src0cs25d-etched.step / src0cs25d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); src0cs25d.step / src0cs25d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (48 pp, sha256 9634f9a14026d87a, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF