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Contents

README

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SQD19P06-60L-GE3-VB

VBsemi Elec · MOSFETs · TO-252

SQD19P06-60L-GE3-VB from VBsemi Elec, in a TO-252. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate terminal of the P-channel MOSFET, rated for a gate-source voltage of ±20 V maximum with a threshold of -1 V to -3 V.
2 D passive Drain terminal, connected internally to the mounting tab, rated for VDS of -60 V and continuous drain current of -35 A at TC = 25 °C.
3 S passive Source terminal of the P-channel MOSFET, with the body diode continuous current rated at -20 A.

Key specifications

Parameter Value
Manufacturer VBsemi Elec
Package TO-252
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: SQD19P06-60L-GE3-VB
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: TO-252 (KiCad packages3D, STEP)
  • 3D model files: sqd19p06-60l-ge3-vb-etched.step / sqd19p06-60l-ge3-vb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sqd19p06-60l-ge3-vb.step / sqd19p06-60l-ge3-vb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: VBsemi Elec datasheet (8 pp, sha256 f006ab48ab2007a5, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF