# SQ9407EY-T1_GE3

**Vishay Intertech** · MOSFETs · SO-8

SQ9407EY-T1_GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET, tied internally with source pins 2 and 3. |
| 2 | S | passive | Source of the P-channel MOSFET, tied internally with source pins 1 and 3. |
| 3 | S | passive | Source of the P-channel MOSFET, tied internally with source pins 1 and 2. |
| 4 | G | input | Gate of the P-channel MOSFET; VGS limit is ±20 V with threshold of -1.5 to -2.5 V. |
| 5 | D | passive | Drain of the P-channel MOSFET, connected with drain pins 6, 7 and 8; VDS rating -60 V. |
| 6 | D | passive | Drain of the P-channel MOSFET, connected with drain pins 5, 7 and 8; VDS rating -60 V. |
| 7 | D | passive | Drain of the P-channel MOSFET, connected with drain pins 5, 6 and 8; VDS rating -60 V. |
| 8 | D | passive | Drain of the P-channel MOSFET, connected with drain pins 5, 6 and 7; VDS rating -60 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SO-8 |
| Category | Triode/MOS Tube/Transistor |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDS |  |  | -60 | V | TC = 25 °C | 1 |
| Gate-source voltage | VGS | -20 |  | 20 | V | TC = 25 °C | 1 |
| Continuous drain current | ID |  |  | -4.6 | A | TC = 25 °C | 1 |
| Continuous drain current | ID |  |  | -2.6 | A | TC = 125 °C | 1 |
| Continuous source current (diode conduction) | IS |  |  | -3.4 | A | TC = 25 °C | 1 |
| Pulsed drain current | IDM |  |  | -18.5 | A | TC = 25 °C | 1 |
| Single pulse avalanche current | IAS |  |  | -20 | A | L = 0.1 mH | 1 |
| Single pulse avalanche energy | EAS |  |  | 20 | mJ | L = 0.1 mH | 1 |
| Maximum power dissipation | PD |  |  | 3.75 | W | TC = 25 °C | 1 |
| Maximum power dissipation | PD |  |  | 1.25 | W | TC = 125 °C | 1 |
| Operating junction and storage temperature range | TJ, Tstg | -55 |  | 175 | °C |  | 1 |
| Junction-to-ambient thermal resistance | RthJA |  |  | 100 | °C/W | PCB mount | 1 |
| Junction-to-case (drain) thermal resistance | RthJF |  |  | 40 | °C/W |  | 1 |
| Drain-source breakdown voltage | VDS | -60 |  |  | V | VGS = 0 V, ID = -250 μA | 2 |
| Gate-source threshold voltage | VGS(th) | -1.5 | -2 | -2.5 | V | VDS = VGS, ID = -250 μA | 2 |
| Gate-source leakage | IGSS | -100 |  | 100 | nA | VDS = 0 V, VGS = ± 20 V | 2 |
| Zero gate voltage drain current | IDSS |  |  | -1 | μA | VGS = 0 V, VDS = -60 V | 2 |
| Zero gate voltage drain current | IDSS |  |  | -50 | μA | VGS = 0 V, VDS = -60 V, TJ = 125 °C | 2 |
| Zero gate voltage drain current | IDSS |  |  | -150 | μA | VGS = 0 V, VDS = -60 V, TJ = 175 °C | 2 |
| On-state drain current | ID(on) | -12 |  |  | A | VGS = -10 V, VDS ≤ -5 V | 2 |
| Drain-source on-state resistance | RDS(on) |  | 0.087 | 0.115 | Ω | VGS = -4.5 V, ID = -2.5 A | 2 |
| Drain-source on-state resistance | RDS(on) |  | 0.067 | 0.085 | Ω | VGS = -10 V, ID = -3.5 A | 2 |
| Drain-source on-state resistance | RDS(on) |  |  | 0.143 | Ω | VGS = -10 V, ID = -3.5 A, TJ = 125 °C | 2 |
| Drain-source on-state resistance | RDS(on) |  |  | 0.176 | Ω | VGS = -10 V, ID = -3.5 A, TJ = 175 °C | 2 |
| Input capacitance | Ciss |  | 912 | 1140 | pF | VGS = 0 V, VDS = -30 V, f = 1 MHz | 2 |
| Output capacitance | Coss |  | 100 | 125 | pF | VGS = 0 V, VDS = -30 V, f = 1 MHz | 2 |
| Reverse transfer capacitance | Crss |  | 60 | 75 | pF | VGS = 0 V, VDS = -30 V, f = 1 MHz | 2 |
| Total gate charge | Qg |  | 26.5 | 40 | nC | VGS = -10 V, VDS = -30 V, ID = -4.3 A | 2 |
| Gate resistance | Rg | 3.5 | 7.1 | 10.7 | Ω | f = 1 MHz | 2 |
| Turn-on delay time | td(on) |  | 11 | 17 | ns | VDD = -30 V, RL = 8.8 Ω, ID ≅ -3.4 A, VGEN = -10 V, Rg = 1 Ω | 2 |
| Rise time | tr |  | 13 | 20 | ns | VDD = -30 V, RL = 8.8 Ω, ID ≅ -3.4 A, VGEN = -10 V, Rg = 1 Ω | 2 |
| Turn-off delay time | td(off) |  | 36 | 54 | ns | VDD = -30 V, RL = 8.8 Ω, ID ≅ -3.4 A, VGEN = -10 V, Rg = 1 Ω | 2 |
| Fall time | tf |  | 8 | 12 | ns | VDD = -30 V, RL = 8.8 Ω, ID ≅ -3.4 A, VGEN = -10 V, Rg = 1 Ω | 2 |
| Pulsed source-drain current | ISM |  |  | -18.5 | A |  | 2 |
| Diode forward voltage | VSD |  | -0.84 | -1.1 | V | IF = -3 A, VGS = 0 V | 2 |
| Forward transconductance | gfs |  | 10 |  | S | VDS = -15 V, ID = -3.5 A | 2 |
| Gate-source charge | Qgs |  | 3.8 |  | nC | VGS = -10 V, VDS = -30 V, ID = -4.3 A | 2 |
| Gate-drain charge | Qgd |  | 5.8 |  | nC | VGS = -10 V, VDS = -30 V, ID = -4.3 A | 2 |

## CAD (KiCad official)

- Symbol: `SQ9407EY-T1_GE3`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `sq9407ey-t1-ge3-etched.step` / `sq9407ey-t1-ge3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sq9407ey-t1-ge3.step` / `sq9407ey-t1-ge3.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Vishay Intertech datasheet](docs/sq9407ey-t1-ge3-datasheet.pdf) (9 pp, sha256 `cd949cfebfc8e930`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sq9407ey-t1-ge3-datasheet.pdf)