component
SQ4940AEY-T1_GE3
Public Made by Adomby adom
Vishay Intertech MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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|---|---|
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| sq4940aey-t1-ge3-etched.glb | 17d ago |
| sq4940aey-t1-ge3-etched.step | 17d ago |
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SQ4940AEY-T1_GE3
Vishay Intertech · MOSFETs · SO-8
SQ4940AEY-T1_GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source terminal of N-channel MOSFET 1 in this dual 40 V device; absolute maximum VDS is 40 V and VGS is ±20 V. |
| 2 | G1 | input | Gate terminal of N-channel MOSFET 1; gate-source voltage is limited to ±20 V. |
| 3 | S2 | passive | Source terminal of N-channel MOSFET 2 in this dual 40 V device; absolute maximum VDS is 40 V and VGS is ±20 V. |
| 4 | G2 | input | Gate terminal of N-channel MOSFET 2; gate-source voltage is limited to ±20 V. |
| 5 | D2 | passive | Drain terminal of N-channel MOSFET 2; device drain-source voltage rating is 40 V. |
| 6 | D2 | passive | Drain terminal of N-channel MOSFET 2 (second drain pin); device drain-source voltage rating is 40 V. |
| 7 | D1 | passive | Drain terminal of N-channel MOSFET 1; device drain-source voltage rating is 40 V. |
| 8 | D1 | passive | Drain terminal of N-channel MOSFET 1 (second drain pin); device drain-source voltage rating is 40 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | 40 | V | 1 | |||
| Gate-Source Voltage | VGS | -20 | 20 | V | 1 | ||
| Continuous Drain Current | ID | 8 | A | TC = 25 °C | 1 | ||
| Continuous Drain Current | ID | 5.3 | A | TC = 125 °C | 1 | ||
| Continuous Source Current (Diode Conduction) | IS | 3.6 | A | 1 | |||
| Pulsed Drain Current | IDM | 32 | A | 1 | |||
| Single Pulse Avalanche Current | IAS | 17 | A | L = 0.1 mH | 1 | ||
| Single Pulse Avalanche Energy | EAS | 15 | mJ | 1 | |||
| Maximum Power Dissipation | PD | 4 | W | TC = 25 °C | 1 | ||
| Maximum Power Dissipation | PD | 1.3 | W | TC = 125 °C | 1 | ||
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | 175 | °C | 1 | ||
| Junction-to-Ambient | RthJA | 112 | °C/W | PCB Mount, 1" square PCB (FR-4 material) | 1 | ||
| Junction-to-Foot (Drain) | RthJF | 38 | °C/W | 1 | |||
| Drain-Source Breakdown Voltage | VDS | 40 | V | VGS = 0 V, ID = 250 μA | 2 | ||
| Gate-Source Threshold Voltage | VGS(th) | 1.5 | 2 | 2.5 | V | VDS = VGS, ID = 250 μA | 2 |
| Gate-Source Leakage | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ± 20 V | 2 | |
| Zero Gate Voltage Drain Current | IDSS | 1 | μA | VGS = 0 V, VDS = 40 V | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | 50 | μA | VGS = 0 V, VDS = 40 V, TJ = 55 °C | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | 150 | μA | VGS = 0 V, VDS = 40 V, TJ = 175 °C | 2 | ||
| On-State Drain Current | ID(on) | 30 | A | VGS = 10 V, VDS5 V (relational sign missing in text) | 2 | ||
| Drain-Source On-State Resistance | RDS(on) | 0.02 | 0.024 | Ω | VGS = 10 V, ID = 5.3 A | 2 | |
| Drain-Source On-State Resistance | RDS(on) | 0.036 | Ω | VGS = 10 V, ID = 5.3 A, TJ = 125 °C | 2 | ||
| Drain-Source On-State Resistance | RDS(on) | 0.043 | Ω | VGS = 10 V, ID = 5.3 A, TJ = 175 °C | 2 | ||
| Drain-Source On-State Resistance | RDS(on) | 0.024 | 0.029 | Ω | VGS = 4.5 V, ID = 4.9 A | 2 | |
| Input Capacitance | Ciss | 593 | 741 | pF | VGS = 0 V, VDS = 20 V, f = 1 MHz | 2 | |
| Output Capacitance | Coss | 103 | 129 | pF | VGS = 0 V, VDS = 20 V, f = 1 MHz | 2 | |
| Reverse Transfer Capacitance | Crss | 44 | 55 | pF | VGS = 0 V, VDS = 20 V, f = 1 MHz | 2 | |
| Total Gate Charge | Qg | 28.4 | 43 | nC | VGS = 10 V, VDS = 20 V, ID = 5.7 A | 2 | |
| Gate Resistance | Rg | 0.5 | 2 | Ω | f = 1 MHz | 2 | |
| Turn-On Delay Time | td(on) | 8 | 12 | ns | VDD = 20 V, RL = 3.5 Ω, ID ≅ 5.7 A, VGEN = 10 V, Rg = 1 Ω | 2 | |
| Rise Time | tr | 13 | 20 | ns | 2 | ||
| Turn-Off Delay Time | td(off) | 20 | 30 | ns | 2 | ||
| Fall Time | tf | 9 | 14 | ns | 2 | ||
| Pulsed Current | ISM | 32 | A | 2 | |||
| Forward Voltage | VSD | 0.75 | 1.1 | V | IF = 3.6 A, VGS = 0 V | 2 |
CAD (KiCad official)
- Symbol:
SQ4940AEY-T1_GE3 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
sq4940aey-t1-ge3-etched.step/sq4940aey-t1-ge3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sq4940aey-t1-ge3.step/sq4940aey-t1-ge3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (9 pp, sha256
f9d2b91be7568599, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).