component
SQ4917CEY-T1_GE3
Public Made by Adomby adom
Vishay Intertech MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SQ4917CEY-T1_GE3
Vishay Intertech · MOSFETs · SO-8
SQ4917CEY-T1_GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of P-channel MOSFET 1 (leg 1, VDS -60 V, ID -8 A per leg). |
| 2 | G1 | input | Gate of P-channel MOSFET 1, with gate-source voltage limit of ±20 V. |
| 3 | S2 | passive | Source of P-channel MOSFET 2 (leg 2, VDS -60 V, ID -8 A per leg). |
| 4 | G2 | input | Gate of P-channel MOSFET 2, with gate-source voltage limit of ±20 V. |
| 5 | D2 | passive | Drain of P-channel MOSFET 2, tied to pin 6, with drain-source voltage rating of -60 V. |
| 6 | D2 | passive | Drain of P-channel MOSFET 2, tied to pin 5, with drain-source voltage rating of -60 V. |
| 7 | D1 | passive | Drain of P-channel MOSFET 1, tied to pin 8, with drain-source voltage rating of -60 V. |
| 8 | D1 | passive | Drain of P-channel MOSFET 1, tied to pin 7, with drain-source voltage rating of -60 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
SQ4917CEY-T1_GE3 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
sq4917cey-t1-ge3-etched.step/sq4917cey-t1-ge3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sq4917cey-t1-ge3.step/sq4917cey-t1-ge3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (8 pp, sha256
4ae7ebde79603416, retrieved 2026-10-10, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SQ4917CEY-T1_GE3
**Vishay Intertech** · MOSFETs · SO-8
SQ4917CEY-T1_GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of P-channel MOSFET 1 (leg 1, VDS -60 V, ID -8 A per leg). |
| 2 | G1 | input | Gate of P-channel MOSFET 1, with gate-source voltage limit of ±20 V. |
| 3 | S2 | passive | Source of P-channel MOSFET 2 (leg 2, VDS -60 V, ID -8 A per leg). |
| 4 | G2 | input | Gate of P-channel MOSFET 2, with gate-source voltage limit of ±20 V. |
| 5 | D2 | passive | Drain of P-channel MOSFET 2, tied to pin 6, with drain-source voltage rating of -60 V. |
| 6 | D2 | passive | Drain of P-channel MOSFET 2, tied to pin 5, with drain-source voltage rating of -60 V. |
| 7 | D1 | passive | Drain of P-channel MOSFET 1, tied to pin 8, with drain-source voltage rating of -60 V. |
| 8 | D1 | passive | Drain of P-channel MOSFET 1, tied to pin 7, with drain-source voltage rating of -60 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `SQ4917CEY-T1_GE3`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `sq4917cey-t1-ge3-etched.step` / `sq4917cey-t1-ge3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sq4917cey-t1-ge3.step` / `sq4917cey-t1-ge3.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Vishay Intertech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8604371497704714240) (8 pp, sha256 `4ae7ebde79603416`, retrieved 2026-10-10, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sq4917cey-t1-ge3-datasheet.pdf)