# SQ4470EY-T1_GE3

**Vishay Intertech** · MOSFETs · SO-8

SQ4470EY-T1_GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the N-channel MOSFET; the datasheet rates the continuous source (diode) current at IS = 6 A and the pulsed current at ISM = 67 A. |
| 2 | S | passive | Source terminal of the N-channel MOSFET; the datasheet rates the continuous source (diode) current at IS = 6 A and the pulsed current at ISM = 67 A. |
| 3 | S | passive | Source terminal of the N-channel MOSFET; the datasheet rates the continuous source (diode) current at IS = 6 A and the pulsed current at ISM = 67 A. |
| 4 | G | passive | Gate terminal of the N-channel MOSFET; gate-source voltage is rated at ±20 V (VGS). |
| 5 | D | passive | Drain terminal of the N-channel MOSFET; drain-source voltage is rated at 60 V (VDS) and continuous drain current at 16 A with TC = 25 °C. |
| 6 | D | passive | Drain terminal of the N-channel MOSFET; drain-source voltage is rated at 60 V (VDS) and continuous drain current at 16 A with TC = 25 °C. |
| 7 | D | passive | Drain terminal of the N-channel MOSFET; drain-source voltage is rated at 60 V (VDS) and continuous drain current at 16 A with TC = 25 °C. |
| 8 | D | passive | Drain terminal of the N-channel MOSFET; drain-source voltage is rated at 60 V (VDS) and continuous drain current at 16 A with TC = 25 °C. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDS |  |  | 60 | V |  | 1 |
| Gate-source voltage | VGS | -20 |  | 20 | V |  | 1 |
| Continuous drain current | ID |  |  | 16 | A | TC = 25 °C | 1 |
| Continuous drain current | ID |  |  | 9 | A | TC = 125 °C | 1 |
| Continuous source current (diode conduction) | IS |  |  | 6 | A |  | 1 |
| Pulsed drain current | IDM |  |  | 67 | A |  | 1 |
| Single pulse avalanche current | IAS |  |  | 50 | A | L = 0.1 mH | 1 |
| Single pulse avalanche energy | EAS |  |  | 125 | mJ |  | 1 |
| Maximum power dissipation | PD |  |  | 7.1 | W | TC = 25 °C | 1 |
| Maximum power dissipation | PD |  |  | 2.3 | W | TC = 125 °C | 1 |
| Operating junction and storage temperature range | TJ, Tstg | -55 |  | 175 | °C |  | 1 |
| Junction-to-ambient thermal resistance | RthJA |  |  | 80 | °C/W | PCB mount | 1 |
| Junction-to-case (drain) thermal resistance | RthJF |  |  | 21 | °C/W |  | 1 |
| Drain-source breakdown voltage | VDS | 60 |  |  | V | VGS = 0, ID = 250 μA | 2 |
| Gate-source threshold voltage | VGS(th) | 2.5 | 3 | 3.5 |  | VDS = VGS, ID = 250 μA | 2 |
| Gate-source leakage | IGSS | -100 |  | 100 | nA | VDS = 0 V, VGS = ± 20 V | 2 |
| Zero gate voltage drain current | IDSS |  |  | 1 | μA | VGS = 0 V, VDS = 60 V | 2 |
| Zero gate voltage drain current | IDSS |  |  | 50 | μA | VGS = 0 V, VDS = 60 V, TJ = 125 °C | 2 |
| Zero gate voltage drain current | IDSS |  |  | 250 | μA | VGS = 0 V, VDS = 60 V, TJ = 175 °C | 2 |
| On-state drain current | ID(on) | 30 |  |  | A | VGS = 10 V, VDS ≥ 5 V | 2 |
| Drain-source on-state resistance | RDS(on) |  | 0.01 | 0.012 | Ω | VGS = 10 V, ID = 6 A | 2 |
| Drain-source on-state resistance | RDS(on) |  |  | 0.021 | Ω | VGS = 10 V, ID = 6 A, TJ = 125 °C | 2 |
| Drain-source on-state resistance | RDS(on) |  |  | 0.025 | Ω | VGS = 10 V, ID = 6 A, TJ = 175 °C | 2 |
| Drain-source on-state resistance | RDS(on) |  | 0.012 | 0.014 | Ω | VGS = 6 V, ID = 5 A | 2 |
| Input capacitance | Ciss |  | 2531 | 3165 | pF | VGS = 0 V, VDS = 25 V, f = 1 MHz | 2 |
| Output capacitance | Coss |  | 382 | 480 | pF | VGS = 0 V, VDS = 25 V, f = 1 MHz | 2 |
| Reverse transfer capacitance | Crss |  | 153 | 195 | pF | VGS = 0 V, VDS = 25 V, f = 1 MHz | 2 |
| Total gate charge | Qg |  | 45 | 68 | nC | VGS = 10 V, VDS = 30 V, ID = 12 A | 2 |
| Gate resistance | Rg | 0.4 | 0.87 | 1.3 | Ω | f = 1 MHz | 2 |
| Turn-on delay time | td(on) |  | 13 | 20 | ns | VDD = 30 V, RL = 2.5 Ω, ID ≅ 12 A, VGEN = 10 V, Rg = 1 Ω | 2 |
| Rise time | tr |  | 12 | 18 | ns | VDD = 30 V, RL = 2.5 Ω, ID ≅ 12 A, VGEN = 10 V, Rg = 1 Ω | 2 |
| Turn-off delay time | td(off) |  | 25 | 38 | ns | VDD = 30 V, RL = 2.5 Ω, ID ≅ 12 A, VGEN = 10 V, Rg = 1 Ω | 2 |
| Fall time | tf |  | 9 | 14 | ns | VDD = 30 V, RL = 2.5 Ω, ID ≅ 12 A, VGEN = 10 V, Rg = 1 Ω | 2 |
| Pulsed current | ISM |  |  | 67 | A |  | 2 |
| Forward voltage | VSD |  | 0.72 | 1.2 | V | IF = 1.7 A, VGS = 0 | 2 |

## CAD (KiCad official)

- Symbol: `SQ4470EY-T1_GE3`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `sq4470ey-t1-ge3-etched.step` / `sq4470ey-t1-ge3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sq4470ey-t1-ge3.step` / `sq4470ey-t1-ge3.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Vishay Intertech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590892311301865472) (10 pp, sha256 `34ffd180e4e3087f`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sq4470ey-t1-ge3-datasheet.pdf)