component
SQ4401EY-T1_GE3
Public Made by Adomby adom
Vishay Intertech MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SQ4401EY-T1_GE3
Vishay Intertech · MOSFETs · SO-8
SQ4401EY-T1_GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET; continuous source current (diode conduction) is limited to -6.5 A. |
| 2 | S | passive | Source of the P-channel MOSFET, connected in parallel with the other source pins (1, 2, 3). |
| 3 | S | passive | Source of the P-channel MOSFET, connected in parallel with the other source pins (1, 2, 3). |
| 4 | G | input | Gate of the P-channel MOSFET; maximum gate-source voltage is ±20 V with threshold VGS(th) of -1.5 V min to -2.5 V max at ID = -250 µA. |
| 5 | D | passive | Drain of the P-channel MOSFET, rated for VDS of -40 V and continuous drain current of -17.3 A at TC = 25 °C. |
| 6 | D | passive | Drain of the P-channel MOSFET, connected in parallel with the other drain pins (5, 6, 7, 8). |
| 7 | D | passive | Drain of the P-channel MOSFET, connected in parallel with the other drain pins (5, 6, 7, 8). |
| 8 | D | passive | Drain of the P-channel MOSFET, connected in parallel with the other drain pins (5, 6, 7, 8); pulsed drain current is limited to -69 A. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SO-8 |
| Category | Triode/MOS Tube/Transistor |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDS | -40 | V | 1 | |||
| Gate-source voltage | VGS | -20 | 20 | V | 1 | ||
| Continuous drain current | ID | -17.3 | A | TC = 25 °C | 1 | ||
| Continuous drain current | ID | -10 | A | TC = 125 °C | 1 | ||
| Continuous source current (diode conduction) | IS | -6.5 | A | 1 | |||
| Pulsed drain current | IDM | -69 | A | 1 | |||
| Single pulse avalanche current | IAS | -30 | A | L = 0.1 mH | 1 | ||
| Single pulse avalanche energy | EAS | 45 | mJ | 1 | |||
| Maximum power dissipation | PD | 7.14 | W | TC = 25 °C | 1 | ||
| Maximum power dissipation | PD | 2.4 | W | TC = 125 °C | 1 | ||
| Operating junction and storage temperature range | TJ, Tstg | -55 | 175 | °C | 1 | ||
| Junction-to-ambient PCB mount | RthJA | 85 | °C/W | PCB mount | 1 | ||
| Junction-to-foot (drain) | RthJF | 21 | °C/W | 1 | |||
| Drain-source breakdown voltage | VDS | -40 | V | VGS = 0, ID = - 250 μA | 2 | ||
| Gate-source threshold voltage | VGS(th) | -1.5 | -2 | -2.5 | V | VDS = VGS, ID = - 250 μA | 2 |
| Gate-source leakage | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ± 20 V | 2 | |
| Zero gate voltage drain current | IDSS | -1 | μA | VGS = 0 V, VDS = - 40 V | 2 | ||
| Zero gate voltage drain current | IDSS | -50 | μA | VGS = 0 V, VDS = - 40 V, TJ = 125 °C | 2 | ||
| Zero gate voltage drain current | IDSS | -150 | μA | VGS = 0 V, VDS = - 40 V, TJ = 175 °C | 2 | ||
| On-state drain current | ID(on) | -30 | A | VGS = - 10 V VDS- 5 V | 2 | ||
| Drain-source on-state resistance | RDS(on) | 0.011 | 0.014 | Ω | VGS = - 10 V, ID = - 10.5 A | 2 | |
| Drain-source on-state resistance | RDS(on) | 0.02 | Ω | VGS = - 10 V, ID = - 10.5 A, TJ = 125 °C | 2 | ||
| Drain-source on-state resistance | RDS(on) | 0.024 | Ω | VGS = - 10 V, ID = - 10.5 A, TJ = 175 °C | 2 | ||
| Drain-source on-state resistance | RDS(on) | 0.017 | 0.023 | Ω | VGS = - 4.5 V, ID = - 8.7 A | 2 | |
| Input capacitance | Ciss | 3400 | 4250 | pF | VGS = 0 V, VDS = - 20 V, f = 1 MHz | 2 | |
| Output capacitance | Coss | 440 | 550 | pF | VGS = 0 V, VDS = - 20 V, f = 1 MHz | 2 | |
| Reverse transfer capacitance | Crss | 350 | 436 | pF | VGS = 0 V, VDS = - 20 V, f = 1 MHz | 2 | |
| Total gate charge | Qg | 74 | 115 | nC | VGS = - 10 V, VDS = - 20 V, ID = - 10.5 A | 2 | |
| Gate resistance | Rg | 1.16 | 3.21 | Ω | f = 1 MHz | 2 | |
| Turn-on delay time | td(on) | 58 | 85 | ns | VDD = - 15 V, RL = 15, ID - 1 A, VGEN = - 4.5 V, Rg = 6 | 2 | |
| Rise time | tr | 76 | 105 | ns | VDD = - 15 V, RL = 15, ID - 1 A, VGEN = - 4.5 V, Rg = 6 | 2 | |
| Turn-off delay time | td(off) | 67 | 85 | ns | VDD = - 15 V, RL = 15, ID - 1 A, VGEN = - 4.5 V, Rg = 6 | 2 | |
| Fall time | tf | 44 | 55 | ns | VDD = - 15 V, RL = 15, ID - 1 A, VGEN = - 4.5 V, Rg = 6 | 2 | |
| Pulsed current | ISM | -69 | A | 2 | |||
| Forward voltage | VSD | -0.8 | -1.1 | V | IF = - 2.7 A, VGS = 0 | 2 |
CAD (KiCad official)
- Symbol:
SQ4401EY-T1_GE3 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
sq4401ey-t1-ge3-etched.step/sq4401ey-t1-ge3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sq4401ey-t1-ge3.step/sq4401ey-t1-ge3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (8 pp, sha256
69d07e33bd87f9c7, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SQ4401EY-T1_GE3
**Vishay Intertech** · MOSFETs · SO-8
SQ4401EY-T1_GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET; continuous source current (diode conduction) is limited to -6.5 A. |
| 2 | S | passive | Source of the P-channel MOSFET, connected in parallel with the other source pins (1, 2, 3). |
| 3 | S | passive | Source of the P-channel MOSFET, connected in parallel with the other source pins (1, 2, 3). |
| 4 | G | input | Gate of the P-channel MOSFET; maximum gate-source voltage is ±20 V with threshold VGS(th) of -1.5 V min to -2.5 V max at ID = -250 µA. |
| 5 | D | passive | Drain of the P-channel MOSFET, rated for VDS of -40 V and continuous drain current of -17.3 A at TC = 25 °C. |
| 6 | D | passive | Drain of the P-channel MOSFET, connected in parallel with the other drain pins (5, 6, 7, 8). |
| 7 | D | passive | Drain of the P-channel MOSFET, connected in parallel with the other drain pins (5, 6, 7, 8). |
| 8 | D | passive | Drain of the P-channel MOSFET, connected in parallel with the other drain pins (5, 6, 7, 8); pulsed drain current is limited to -69 A. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SO-8 |
| Category | Triode/MOS Tube/Transistor |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDS | -40 | | | V | | 1 |
| Gate-source voltage | VGS | -20 | | 20 | V | | 1 |
| Continuous drain current | ID | -17.3 | | | A | TC = 25 °C | 1 |
| Continuous drain current | ID | -10 | | | A | TC = 125 °C | 1 |
| Continuous source current (diode conduction) | IS | -6.5 | | | A | | 1 |
| Pulsed drain current | IDM | -69 | | | A | | 1 |
| Single pulse avalanche current | IAS | -30 | | | A | L = 0.1 mH | 1 |
| Single pulse avalanche energy | EAS | | | 45 | mJ | | 1 |
| Maximum power dissipation | PD | | | 7.14 | W | TC = 25 °C | 1 |
| Maximum power dissipation | PD | | | 2.4 | W | TC = 125 °C | 1 |
| Operating junction and storage temperature range | TJ, Tstg | -55 | | 175 | °C | | 1 |
| Junction-to-ambient PCB mount | RthJA | | | 85 | °C/W | PCB mount | 1 |
| Junction-to-foot (drain) | RthJF | | | 21 | °C/W | | 1 |
| Drain-source breakdown voltage | VDS | -40 | | | V | VGS = 0, ID = - 250 μA | 2 |
| Gate-source threshold voltage | VGS(th) | -1.5 | -2 | -2.5 | V | VDS = VGS, ID = - 250 μA | 2 |
| Gate-source leakage | IGSS | -100 | | 100 | nA | VDS = 0 V, VGS = ± 20 V | 2 |
| Zero gate voltage drain current | IDSS | | | -1 | μA | VGS = 0 V, VDS = - 40 V | 2 |
| Zero gate voltage drain current | IDSS | | | -50 | μA | VGS = 0 V, VDS = - 40 V, TJ = 125 °C | 2 |
| Zero gate voltage drain current | IDSS | | | -150 | μA | VGS = 0 V, VDS = - 40 V, TJ = 175 °C | 2 |
| On-state drain current | ID(on) | -30 | | | A | VGS = - 10 V VDS- 5 V | 2 |
| Drain-source on-state resistance | RDS(on) | | 0.011 | 0.014 | Ω | VGS = - 10 V, ID = - 10.5 A | 2 |
| Drain-source on-state resistance | RDS(on) | | | 0.02 | Ω | VGS = - 10 V, ID = - 10.5 A, TJ = 125 °C | 2 |
| Drain-source on-state resistance | RDS(on) | | | 0.024 | Ω | VGS = - 10 V, ID = - 10.5 A, TJ = 175 °C | 2 |
| Drain-source on-state resistance | RDS(on) | | 0.017 | 0.023 | Ω | VGS = - 4.5 V, ID = - 8.7 A | 2 |
| Input capacitance | Ciss | | 3400 | 4250 | pF | VGS = 0 V, VDS = - 20 V, f = 1 MHz | 2 |
| Output capacitance | Coss | | 440 | 550 | pF | VGS = 0 V, VDS = - 20 V, f = 1 MHz | 2 |
| Reverse transfer capacitance | Crss | | 350 | 436 | pF | VGS = 0 V, VDS = - 20 V, f = 1 MHz | 2 |
| Total gate charge | Qg | | 74 | 115 | nC | VGS = - 10 V, VDS = - 20 V, ID = - 10.5 A | 2 |
| Gate resistance | Rg | 1.16 | | 3.21 | Ω | f = 1 MHz | 2 |
| Turn-on delay time | td(on) | | 58 | 85 | ns | VDD = - 15 V, RL = 15, ID - 1 A, VGEN = - 4.5 V, Rg = 6 | 2 |
| Rise time | tr | | 76 | 105 | ns | VDD = - 15 V, RL = 15, ID - 1 A, VGEN = - 4.5 V, Rg = 6 | 2 |
| Turn-off delay time | td(off) | | 67 | 85 | ns | VDD = - 15 V, RL = 15, ID - 1 A, VGEN = - 4.5 V, Rg = 6 | 2 |
| Fall time | tf | | 44 | 55 | ns | VDD = - 15 V, RL = 15, ID - 1 A, VGEN = - 4.5 V, Rg = 6 | 2 |
| Pulsed current | ISM | | | -69 | A | | 2 |
| Forward voltage | VSD | | -0.8 | -1.1 | V | IF = - 2.7 A, VGS = 0 | 2 |
## CAD (KiCad official)
- Symbol: `SQ4401EY-T1_GE3`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `sq4401ey-t1-ge3-etched.step` / `sq4401ey-t1-ge3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sq4401ey-t1-ge3.step` / `sq4401ey-t1-ge3.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Vishay Intertech datasheet](docs/sq4401ey-t1-ge3-datasheet.pdf) (8 pp, sha256 `69d07e33bd87f9c7`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sq4401ey-t1-ge3-datasheet.pdf)