# SQ4401CEY-T1_GE3

**Vishay Intertech** · MOSFETs · SO-8

SQ4401CEY-T1_GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the P-channel MOSFET; the datasheet gives continuous source current (diode conduction) as -6.5 A. |
| 2 | S | passive | Source terminal of the P-channel MOSFET; the datasheet gives continuous source current (diode conduction) as -6.5 A. |
| 3 | S | passive | Source terminal of the P-channel MOSFET; the datasheet gives continuous source current (diode conduction) as -6.5 A. |
| 4 | G | input | Gate terminal of the P-channel MOSFET; the gate-source voltage is rated at ±20 V. |
| 5 | D | passive | Drain terminal of the P-channel MOSFET; the drain-source voltage is rated at -40 V. |
| 6 | D | passive | Drain terminal of the P-channel MOSFET; the drain-source voltage is rated at -40 V. |
| 7 | D | passive | Drain terminal of the P-channel MOSFET; the drain-source voltage is rated at -40 V. |
| 8 | D | passive | Drain terminal of the P-channel MOSFET; the drain-source voltage is rated at -40 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDS | -40 |  |  | V |  | 1 |
| Gate-source voltage | VGS | -20 |  | 20 | V |  | 1 |
| Continuous drain current | ID | -17.3 |  |  | A | TC = 25 °C | 1 |
| Continuous drain current | ID | -10 |  |  | A | TC = 125 °C | 1 |
| Continuous source current (diode conduction) | IS | -6.5 |  |  | A |  | 1 |
| Pulsed drain current | IDM | -69 |  |  | A | Pulse test; pulse width 300 μs, duty cycle 2 % | 1 |
| Single pulse avalanche current | IAS | -30 |  |  | A | L = 0.1 mH | 1 |
| Single pulse avalanche energy | EAS |  |  | 45 | mJ |  | 1 |
| Maximum power dissipation | PD |  |  | 7.14 | W | TC = 25 °C | 1 |
| Maximum power dissipation | PD |  |  | 2.4 | W | TC = 125 °C | 1 |
| Operating junction and storage temperature range | TJ, Tstg | -55 |  | 175 | °C |  | 1 |
| Junction-to-ambient thermal resistance | RthJA |  |  | 85 | °C/W | PCB mount (note b) | 1 |
| Junction-to-foot (drain) thermal resistance | RthJF |  |  | 21 | °C/W |  | 1 |
| Drain-source breakdown voltage | VDS | -40 |  |  | V | VGS = 0, ID = -250 μA | 2 |
| Gate-source threshold voltage | VGS(th) | -1.5 | -2 | -2.5 | V | VDS = VGS, ID = -250 μA | 2 |
| Gate-source leakage | IGSS | -100 |  | 100 | nA | VDS = 0 V, VGS = ± 20 V | 2 |
| Zero gate voltage drain current | IDSS |  |  | -1 | μA | VGS = 0 V, VDS = -40 V | 2 |
| Zero gate voltage drain current | IDSS |  |  | -50 | μA | VGS = 0 V, VDS = -40 V, TJ = 125 °C | 2 |
| Zero gate voltage drain current | IDSS |  |  | -150 | μA | VGS = 0 V, VDS = -40 V, TJ = 175 °C | 2 |
| On-state drain current | ID(on) | -30 |  |  | A | VGS = -10 V, VDS-5 V | 2 |
| Drain-source on-state resistance | RDS(on) |  | 0.011 | 0.014 | Ω | VGS = -10 V, ID = -10.5 A | 2 |
| Drain-source on-state resistance | RDS(on) |  |  | 0.02 | Ω | VGS = -10 V, ID = -10.5 A, TJ = 125 °C | 2 |
| Drain-source on-state resistance | RDS(on) |  |  | 0.024 | Ω | VGS = -10 V, ID = -10.5 A, TJ = 175 °C | 2 |
| Drain-source on-state resistance | RDS(on) |  | 0.018 | 0.023 | Ω | VGS = -4.5 V, ID = -8.7 A | 2 |
| Input capacitance | Ciss |  | 3471 | 4250 | pF | VGS = 0 V, VDS = -20 V, f = 1 MHz | 2 |
| Output capacitance | Coss |  | 526 | 580 | pF | VGS = 0 V, VDS = -20 V, f = 1 MHz | 2 |
| Reverse transfer capacitance | Crss |  | 349 | 436 | pF | VGS = 0 V, VDS = -20 V, f = 1 MHz | 2 |
| Total gate charge | Qg |  | 71 | 115 | nC | VGS = -10 V, VDS = -20 V, ID = -10.5 A | 2 |
| Gate resistance | Rg | 0.95 | 1.9 | 3.21 | Ω | f = 1 MHz | 2 |
| Turn-on delay time | td(on) |  | 35 | 85 | ns | VDD = -15 V, RL = 15, ID -1 A, VGEN = -4.5 V, Rg = 6 | 2 |
| Rise time | tr |  | 52 | 105 | ns | VDD = -15 V, RL = 15, ID -1 A, VGEN = -4.5 V, Rg = 6 | 2 |
| Turn-off delay time | td(off) |  | 62 | 85 | ns | VDD = -15 V, RL = 15, ID -1 A, VGEN = -4.5 V, Rg = 6 | 2 |
| Fall time | tf |  | 50 | 55 | ns | VDD = -15 V, RL = 15, ID -1 A, VGEN = -4.5 V, Rg = 6 | 2 |
| Pulsed current | ISM |  |  | -69 | A |  | 2 |
| Forward voltage | VSD |  | -0.75 | -1.1 | V | IF = -2.7 A, VGS = 0 V | 2 |
| Body diode reverse recovery time | trr |  | 30 | 60 | ns | IF = -2.1 A, di/dt = 100 A/μs | 2 |
| Body diode reverse recovery charge | Qrr |  | 36 | 72 | nC |  | 2 |

## CAD (KiCad official)

- Symbol: `SQ4401CEY-T1_GE3`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `sq4401cey-t1-ge3-etched.step` / `sq4401cey-t1-ge3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sq4401cey-t1-ge3.step` / `sq4401cey-t1-ge3.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Vishay Intertech datasheet](https://www.vishay.com/docs/62016/sq4401cey.pdf) (8 pp, sha256 `56ecef7bd74cf61e`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sq4401cey-t1-ge3-datasheet.pdf)