# SQ4182EY-T1_GE3

**Vishay Intertech** · MOSFETs · SOIC-8

SQ4182EY-T1_GE3 from Vishay Intertech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the N-channel MOSFET (pin 1 of the SO-8 single package). |
| 2 | S | passive | Source of the N-channel MOSFET (pin 2 of the SO-8 single package). |
| 3 | S | passive | Source of the N-channel MOSFET (pin 3 of the SO-8 single package). |
| 4 | G | input | Gate of the N-channel MOSFET, with a maximum gate-source voltage of ±20 V. |
| 5 | D | passive | Drain of the N-channel MOSFET, rated for 30 V drain-source voltage. |
| 6 | D | passive | Drain of the N-channel MOSFET, rated for 30 V drain-source voltage. |
| 7 | D | passive | Drain of the N-channel MOSFET, rated for 30 V drain-source voltage. |
| 8 | D | passive | Drain of the N-channel MOSFET, rated for 30 V drain-source voltage. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SOIC-8 |
| Category | Triode/MOS Tube/Transistor |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDS |  |  | 30 | V | TC = 25 °C | 1 |
| Gate-source voltage | VGS | -20 |  | 20 | V | TC = 25 °C | 1 |
| Continuous drain current | ID |  |  | 32 | A | TC = 25 °C, package limited | 1 |
| Continuous drain current | ID |  |  | 18 | A | TC = 125 °C | 1 |
| Continuous source current (diode conduction) | IS |  |  | 6.4 | A |  | 1 |
| Pulsed drain current | IDM |  |  | 100 | A | Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 % | 1 |
| Single pulse avalanche current | IAS |  |  | 60 | A | L = 0.1 mH | 1 |
| Single pulse avalanche energy | EAS |  |  | 180 | mJ | L = 0.1 mH | 1 |
| Maximum power dissipation | PD |  |  | 7.1 | W | TC = 25 °C | 1 |
| Maximum power dissipation | PD |  |  | 2.3 | W | TC = 125 °C | 1 |
| Operating junction and storage temperature range | TJ, Tstg | -55 |  | 175 | °C |  | 1 |
| Junction-to-ambient thermal resistance | RthJA |  |  | 80 | °C/W | PCB mount, 1" square PCB (FR4) | 1 |
| Junction-to-foot (drain) thermal resistance | RthJF |  |  | 21 | °C/W |  | 1 |
| Drain-source breakdown voltage | VDS | 30 |  |  | V | VGS = 0 V, ID = 250 μA | 2 |
| Gate-source threshold voltage | VGS(th) | 1.5 | 2 | 2.5 | V | VDS = VGS, ID = 250 μA | 2 |
| Gate-source leakage | IGSS | -100 |  | 100 | nA | VDS = 0 V, VGS = ± 20 V | 2 |
| Zero gate voltage drain current | IDSS |  |  | 1 | μA | VGS = 0 V, VDS = 30 V | 2 |
| Zero gate voltage drain current | IDSS |  |  | 50 | μA | VGS = 0 V, VDS = 30 V, TJ = 125 °C | 2 |
| Zero gate voltage drain current | IDSS |  |  | 250 | μA | VGS = 0 V, VDS = 30 V, TJ = 175 °C | 2 |
| On-state drain current | ID(on) | 20 |  |  | A | VGS = 10 V, VDS ≥ 5 V | 2 |
| Drain-source on-state resistance | RDS(on) |  | 0.0031 | 0.0038 | Ω | VGS = 10 V, ID = 14 A | 2 |
| Drain-source on-state resistance | RDS(on) |  |  | 0.006 | Ω | VGS = 10 V, ID = 14 A, TJ = 125 °C | 2 |
| Drain-source on-state resistance | RDS(on) |  |  | 0.007 | Ω | VGS = 10 V, ID = 14 A, TJ = 175 °C | 2 |
| Drain-source on-state resistance | RDS(on) |  | 0.004 | 0.005 | Ω | VGS = 4.5 V, ID = 10 A | 2 |
| Input capacitance | Ciss |  | 4313 | 5400 | pF | VGS = 0 V, VDS = 15 V, f = 1 MHz | 2 |
| Output capacitance | Coss |  | 868 | 1090 | pF | VGS = 0 V, VDS = 15 V, f = 1 MHz | 2 |
| Reverse transfer capacitance | Crss |  | 305 | 390 | pF | VGS = 0 V, VDS = 15 V, f = 1 MHz | 2 |
| Total gate charge | Qg |  | 72 | 110 | nC | VGS = 10 V, VDS = 15 V, ID = 20 A | 2 |
| Gate resistance | Rg | 0.9 | 1.8 | 4.9 | Ω | f = 1 MHz | 2 |
| Turn-on delay time | td(on) |  | 16 | 24 | ns | VDD = 15 V, RL = 1.5 Ω, ID ≅ 10 A, VGEN = 10 V, Rg = 1 Ω | 2 |
| Rise time | tr |  | 10 | 15 | ns | VDD = 15 V, RL = 1.5 Ω, ID ≅ 10 A, VGEN = 10 V, Rg = 1 Ω | 2 |
| Turn-off delay time | td(off) |  | 57 | 86 | ns | VDD = 15 V, RL = 1.5 Ω, ID ≅ 10 A, VGEN = 10 V, Rg = 1 Ω | 2 |
| Fall time | tf |  | 8 | 12 | ns | VDD = 15 V, RL = 1.5 Ω, ID ≅ 10 A, VGEN = 10 V, Rg = 1 Ω | 2 |
| Pulsed source current | ISM |  |  | 100 | A |  | 2 |
| Forward voltage | VSD |  | 0.75 | 1.2 | V | IF = 10 A, VGS = 0 V | 2 |
| Forward transconductance | gfs |  | 107 |  | S | VDS = 15 V, ID = 14 A | 2 |
| Gate-source charge | Qgs |  | 14 |  | nC | VGS = 10 V, VDS = 15 V, ID = 20 A | 2 |
| Gate-drain charge | Qgd |  | 8 |  | nC | VGS = 10 V, VDS = 15 V, ID = 20 A | 2 |

## CAD (KiCad official)

- Symbol: `SQ4182EY-T1_GE3`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `sq4182ey-t1-ge3-etched.step` / `sq4182ey-t1-ge3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sq4182ey-t1-ge3.step` / `sq4182ey-t1-ge3.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Vishay Intertech datasheet](docs/sq4182ey-t1-ge3-datasheet.pdf) (9 pp, sha256 `9e2bb791dde2ddef`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sq4182ey-t1-ge3-datasheet.pdf)