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SQ4064EY-T1_GE3

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Vishay Intertech MOSFETs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SQ4064EY-T1_GE3

Vishay Intertech · MOSFETs · SOIC-8

SQ4064EY-T1_GE3 from Vishay Intertech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source of the N-channel MOSFET, tied to pins 2 and 3 (SO-8 single).
2 S passive Source of the N-channel MOSFET, tied to pins 1 and 3 (SO-8 single).
3 S passive Source of the N-channel MOSFET, tied to pins 1 and 2 (SO-8 single).
4 G input Gate of the N-channel MOSFET, with VGS rated ±20 V and threshold of 1.5 to 2.5 V.
5 D passive Drain of the MOSFET, tied to pins 6, 7 and 8, with VDS rated 60 V.
6 D passive Drain of the MOSFET, tied to pins 5, 7 and 8, with VDS rated 60 V.
7 D passive Drain of the MOSFET, tied to pins 5, 6 and 8, with VDS rated 60 V.
8 D passive Drain of the MOSFET, tied to pins 5, 6 and 7, with VDS rated 60 V.

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package SOIC-8
Category Triode/MOS Tube/Transistor
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-source voltage VDS 60 V TC = 25 °C 1
Gate-source voltage VGS -20 20 V TC = 25 °C 1
Continuous drain current ID 12 A TC = 25 °C 1
Continuous drain current ID 6.9 A TC = 125 °C 1
Continuous source current (diode conduction) IS 6.2 A 1
Pulsed drain current IDM 25 A Pulse test 1
Single pulse avalanche current IAS 31 A L = 0.1 mH 1
Single pulse avalanche energy EAS 26 mJ L = 0.1 mH 1
Maximum power dissipation PD 6.8 W TC = 25 °C 1
Maximum power dissipation PD 2.2 W TC = 125 °C 1
Operating junction and storage temperature range TJ, Tstg -55 175 °C 1
Junction-to-ambient thermal resistance RthJA 85 °C/W PCB mount 1
Junction-to-foot (drain) thermal resistance RthJF 22 °C/W 1
Drain-source breakdown voltage VDS 60 V VGS = 0, ID = 250 μA 2
Gate-source threshold voltage VGS(th) 1.5 2 2.5 V VDS = VGS, ID = 250 μA 2
Gate-source leakage IGSS -100 100 nA VDS = 0 V, VGS = ± 20 V 2
Zero gate voltage drain current IDSS 1 μA VGS = 0 V, VDS = 60 V 2
Zero gate voltage drain current IDSS 50 μA VGS = 0 V, VDS = 60 V, TJ = 125 °C 2
Zero gate voltage drain current IDSS 150 μA VGS = 0 V, VDS = 60 V, TJ = 175 °C 2
On-state drain current ID(on) 30 A VGS = 10 V, VDS ≥ 5 V 2
Drain-source on-state resistance RDS(on) 0.0165 0.0198 Ω VGS = 10 V, ID = 6.1 A 2
Drain-source on-state resistance RDS(on) 0.035 Ω VGS = 10 V, ID = 6.1 A, TJ = 125 °C 2
Drain-source on-state resistance RDS(on) 0.044 Ω VGS = 10 V, ID = 6.1 A, TJ = 175 °C 2
Drain-source on-state resistance RDS(on) 0.0177 0.0212 Ω VGS = 4.5 V, ID = 5.9 A 2
Input capacitance Ciss 1677 2096 pF VGS = 0 V, VDS = 25 V, f = 1 MHz 2
Output capacitance Coss 142 178 pF VGS = 0 V, VDS = 25 V, f = 1 MHz 2
Reverse transfer capacitance Crss 58 73 pF VGS = 0 V, VDS = 25 V, f = 1 MHz 2
Total gate charge Qg 29 43 nC VGS = 10 V, VDS = 30 V, ID = 6 A 2
Gate resistance Rg 0.4 0.8 1.6 Ω f = 1 MHz 2
Turn-on delay time td(on) 16 24 ns VDD = 30 V, RL = 30 Ω, VGEN = 10 V, Rg = 1 Ω 2
Rise time tr 9.5 14 ns VDD = 30 V, RL = 30 Ω, VGEN = 10 V, Rg = 1 Ω 2
Turn-off delay time td(off) 33 49 ns VDD = 30 V, RL = 30 Ω, VGEN = 10 V, Rg = 1 Ω 2
Fall time tf 13 22 ns VDD = 30 V, RL = 30 Ω, VGEN = 10 V, Rg = 1 Ω 2
Pulsed source-drain current ISM 48 A 2
Forward voltage VSD 0.8 1.2 V IF = 1.7 A, VGS = 0 2
Forward transconductance gfs 85 S VDS = 15 V, ID = 6.1 A 2
Gate-source charge Qgs 5.5 nC VGS = 10 V, VDS = 30 V, ID = 6 A 2
Gate-drain charge Qgd 3.9 nC VGS = 10 V, VDS = 30 V, ID = 6 A 2

CAD (KiCad official)

  • Symbol: SQ4064EY-T1_GE3
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: sq4064ey-t1-ge3-etched.step / sq4064ey-t1-ge3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sq4064ey-t1-ge3.step / sq4064ey-t1-ge3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (9 pp, sha256 aeec56f654377c2c, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF