component
SQ3426CEV-T1_GE3
Public Made by Adomby adom
Vishay Intertech MOSFETs, TSOP-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SQ3426CEV-T1_GE3
Vishay Intertech · MOSFETs · TSOP-6
SQ3426CEV-T1_GE3 from Vishay Intertech, in a TSOP-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D | passive | Drain of the N-channel MOSFET, rated for VDS 60 V and continuous ID 7 A at TC = 25 °C, tied internally with pins 2, 5 and 6. |
| 2 | D | passive | Drain of the N-channel MOSFET, rated for VDS 60 V and continuous ID 7 A at TC = 25 °C, tied internally with pins 1, 5 and 6. |
| 3 | G | input | Gate of the N-channel MOSFET, with VGS maximum of ±20 V and threshold VGS(th) of 1.5 V min to 2.5 V max at ID = 250 μA. |
| 4 | S | passive | Source of the N-channel MOSFET, with continuous source (body diode) current IS of 6 A. |
| 5 | D | passive | Drain of the N-channel MOSFET, rated for VDS 60 V and continuous ID 7 A at TC = 25 °C, tied internally with pins 1, 2 and 6. |
| 6 | D | passive | Drain of the N-channel MOSFET, rated for VDS 60 V and continuous ID 7 A at TC = 25 °C, tied internally with pins 1, 2 and 5. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | TSOP-6 |
| Category | Transistors/Thyristors |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDS | 60 | V | TC = 25 °C | 1 | ||
| Gate-source voltage | VGS | -20 | 20 | V | TC = 25 °C | 1 | |
| Continuous drain current | ID | 7 | A | TC = 25 °C | 1 | ||
| Continuous drain current | ID | 4 | A | TC = 125 °C | 1 | ||
| Continuous source current (diode conduction) | IS | 6 | A | TC = 25 °C | 1 | ||
| Pulsed drain current | IDM | 29 | A | Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 % | 1 | ||
| Single pulse avalanche current | IAS | 10 | A | L = 0.1 mH | 1 | ||
| Single pulse avalanche energy | EAS | 5 | mJ | L = 0.1 mH | 1 | ||
| Maximum power dissipation | PD | 5 | W | TC = 25 °C | 1 | ||
| Maximum power dissipation | PD | 1.6 | W | TC = 125 °C | 1 | ||
| Operating junction and storage temperature range | TJ, Tstg | -55 | 175 | °C | 1 | ||
| Junction to ambient | RthJA | 110 | °C/W | PCB mount, 1" square PCB (FR4) | 1 | ||
| Junction to foot (drain) | RthJF | 30 | °C/W | 1 | |||
| Drain-source breakdown voltage | VDS | 60 | V | VGS = 0, ID = 250 μA | 2 | ||
| Gate-source threshold voltage | VGS(th) | 1.5 | 2 | 2.5 | V | VDS = VGS, ID = 250 μA | 2 |
| Gate-source leakage | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ± 12 V | 2 | |
| Gate-source leakage | IGSS | -300 | 300 | nA | VDS = 0 V, VGS = ± 20 V | 2 | |
| Zero gate voltage drain current | IDSS | 1 | μA | VGS = 0 V, VDS = 60 V | 2 | ||
| Zero gate voltage drain current | IDSS | 50 | μA | VGS = 0 V, VDS = 60 V, TJ = 125 °C | 2 | ||
| Zero gate voltage drain current | IDSS | 150 | μA | VGS = 0 V, VDS = 60 V, TJ = 175 °C | 2 | ||
| On-state drain current | ID(on) | 10 | A | VGS = 10 V, VDS ≥ 5 V | 2 | ||
| Drain-source on-state resistance | RDS(on) | 0.034 | 0.042 | Ω | VGS = 10 V, ID = 5 A | 2 | |
| Drain-source on-state resistance | RDS(on) | 0.073 | Ω | VGS = 10 V, ID = 5 A, TJ = 125 °C | 2 | ||
| Drain-source on-state resistance | RDS(on) | 0.092 | Ω | VGS = 10 V, ID = 5 A, TJ = 175 °C | 2 | ||
| Drain-source on-state resistance | RDS(on) | 0.037 | 0.063 | Ω | VGS = 4.5 V, ID = 4 A | 2 | |
| Forward transconductance | gfs | 21 | S | VDS = 15 V, ID = 4 A | 2 | ||
| Input Capacitance | Ciss | 718 | 790 | pF | VGS = 0 V, VDS = 30 V, f = 1 MHz | 2 | |
| Output Capacitance | Coss | 75 | 110 | pF | VGS = 0 V, VDS = 30 V, f = 1 MHz | 2 | |
| Reverse Transfer Capacitance | Crss | 29 | 70 | pF | VGS = 0 V, VDS = 30 V, f = 1 MHz | 2 | |
| Total Gate Charge | Qg | 6.8 | 12 | nC | VGS = 4.5 V, VDS = 30 V, ID = 4 A | 2 | |
| Gate-Source Charge | Qgs | 2.9 | nC | VGS = 4.5 V, VDS = 30 V, ID = 4 A | 2 | ||
| Gate-Drain Charge | Qgd | 2 | nC | VGS = 4.5 V, VDS = 30 V, ID = 4 A | 2 | ||
| Gate Resistance | Rg | 1.9 | 3.1 | 5.7 | Ω | f = 1 MHz | 2 |
| Turn-On Delay Time | td(on) | 9 | 14 | ns | VDD = 30 V, RL = 7.5 Ω, ID ≅ 4 A, VGEN = 10 V, Rg = 1 Ω | 2 | |
| Rise Time | tr | 3 | 18 | ns | VDD = 30 V, RL = 7.5 Ω, ID ≅ 4 A, VGEN = 10 V, Rg = 1 Ω | 2 | |
| Turn-Off Delay Time | td(off) | 19 | 29 | ns | VDD = 30 V, RL = 7.5 Ω, ID ≅ 4 A, VGEN = 10 V, Rg = 1 Ω | 2 | |
| Fall Time | tf | 4 | 11 | ns | VDD = 30 V, RL = 7.5 Ω, ID ≅ 4 A, VGEN = 10 V, Rg = 1 Ω | 2 | |
| Pulsed current (diode) | ISM | 29 | A | 2 | |||
| Forward voltage | VSD | 0.77 | 1.2 | V | IF = 1.6 A, VGS = 0 V | 2 | |
| Body diode reverse recovery time | trr | 19 | 38 | ns | IF = 4 A, di/dt = 100 A/μs | 2 | |
| Body diode reverse recovery charge | Qrr | 18 | 36 | nC | IF = 4 A, di/dt = 100 A/μs | 2 | |
| Reverse recovery fall time | ta | 15 | ns | IF = 4 A, di/dt = 100 A/μs | 2 | ||
| Reverse recovery rise time | tb | 4 | ns | IF = 4 A, di/dt = 100 A/μs | 2 | ||
| Body diode peak reverse recovery current | IRM(REC) | -2.1 | A | IF = 4 A, di/dt = 100 A/μs | 2 |
CAD (KiCad official)
- Symbol:
SQ3426CEV-T1_GE3 - Footprint:
Package_SO:TSOP-6_1.65x3.05mm_P0.95mm - 3D model: TSOP-6 (KiCad packages3D, STEP)
- 3D model files:
sq3426cev-t1-ge3-etched.step/sq3426cev-t1-ge3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sq3426cev-t1-ge3.step/sq3426cev-t1-ge3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (9 pp, sha256
952d69cf336454e7, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SQ3426CEV-T1_GE3
**Vishay Intertech** · MOSFETs · TSOP-6
SQ3426CEV-T1_GE3 from Vishay Intertech, in a TSOP-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D | passive | Drain of the N-channel MOSFET, rated for VDS 60 V and continuous ID 7 A at TC = 25 °C, tied internally with pins 2, 5 and 6. |
| 2 | D | passive | Drain of the N-channel MOSFET, rated for VDS 60 V and continuous ID 7 A at TC = 25 °C, tied internally with pins 1, 5 and 6. |
| 3 | G | input | Gate of the N-channel MOSFET, with VGS maximum of ±20 V and threshold VGS(th) of 1.5 V min to 2.5 V max at ID = 250 μA. |
| 4 | S | passive | Source of the N-channel MOSFET, with continuous source (body diode) current IS of 6 A. |
| 5 | D | passive | Drain of the N-channel MOSFET, rated for VDS 60 V and continuous ID 7 A at TC = 25 °C, tied internally with pins 1, 2 and 6. |
| 6 | D | passive | Drain of the N-channel MOSFET, rated for VDS 60 V and continuous ID 7 A at TC = 25 °C, tied internally with pins 1, 2 and 5. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | TSOP-6 |
| Category | Transistors/Thyristors |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDS | | | 60 | V | TC = 25 °C | 1 |
| Gate-source voltage | VGS | -20 | | 20 | V | TC = 25 °C | 1 |
| Continuous drain current | ID | | | 7 | A | TC = 25 °C | 1 |
| Continuous drain current | ID | | | 4 | A | TC = 125 °C | 1 |
| Continuous source current (diode conduction) | IS | | | 6 | A | TC = 25 °C | 1 |
| Pulsed drain current | IDM | | | 29 | A | Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 % | 1 |
| Single pulse avalanche current | IAS | | | 10 | A | L = 0.1 mH | 1 |
| Single pulse avalanche energy | EAS | | | 5 | mJ | L = 0.1 mH | 1 |
| Maximum power dissipation | PD | | | 5 | W | TC = 25 °C | 1 |
| Maximum power dissipation | PD | | | 1.6 | W | TC = 125 °C | 1 |
| Operating junction and storage temperature range | TJ, Tstg | -55 | | 175 | °C | | 1 |
| Junction to ambient | RthJA | | | 110 | °C/W | PCB mount, 1" square PCB (FR4) | 1 |
| Junction to foot (drain) | RthJF | | | 30 | °C/W | | 1 |
| Drain-source breakdown voltage | VDS | 60 | | | V | VGS = 0, ID = 250 μA | 2 |
| Gate-source threshold voltage | VGS(th) | 1.5 | 2 | 2.5 | V | VDS = VGS, ID = 250 μA | 2 |
| Gate-source leakage | IGSS | -100 | | 100 | nA | VDS = 0 V, VGS = ± 12 V | 2 |
| Gate-source leakage | IGSS | -300 | | 300 | nA | VDS = 0 V, VGS = ± 20 V | 2 |
| Zero gate voltage drain current | IDSS | | | 1 | μA | VGS = 0 V, VDS = 60 V | 2 |
| Zero gate voltage drain current | IDSS | | | 50 | μA | VGS = 0 V, VDS = 60 V, TJ = 125 °C | 2 |
| Zero gate voltage drain current | IDSS | | | 150 | μA | VGS = 0 V, VDS = 60 V, TJ = 175 °C | 2 |
| On-state drain current | ID(on) | 10 | | | A | VGS = 10 V, VDS ≥ 5 V | 2 |
| Drain-source on-state resistance | RDS(on) | | 0.034 | 0.042 | Ω | VGS = 10 V, ID = 5 A | 2 |
| Drain-source on-state resistance | RDS(on) | | | 0.073 | Ω | VGS = 10 V, ID = 5 A, TJ = 125 °C | 2 |
| Drain-source on-state resistance | RDS(on) | | | 0.092 | Ω | VGS = 10 V, ID = 5 A, TJ = 175 °C | 2 |
| Drain-source on-state resistance | RDS(on) | | 0.037 | 0.063 | Ω | VGS = 4.5 V, ID = 4 A | 2 |
| Forward transconductance | gfs | | 21 | | S | VDS = 15 V, ID = 4 A | 2 |
| Input Capacitance | Ciss | | 718 | 790 | pF | VGS = 0 V, VDS = 30 V, f = 1 MHz | 2 |
| Output Capacitance | Coss | | 75 | 110 | pF | VGS = 0 V, VDS = 30 V, f = 1 MHz | 2 |
| Reverse Transfer Capacitance | Crss | | 29 | 70 | pF | VGS = 0 V, VDS = 30 V, f = 1 MHz | 2 |
| Total Gate Charge | Qg | | 6.8 | 12 | nC | VGS = 4.5 V, VDS = 30 V, ID = 4 A | 2 |
| Gate-Source Charge | Qgs | | 2.9 | | nC | VGS = 4.5 V, VDS = 30 V, ID = 4 A | 2 |
| Gate-Drain Charge | Qgd | | 2 | | nC | VGS = 4.5 V, VDS = 30 V, ID = 4 A | 2 |
| Gate Resistance | Rg | 1.9 | 3.1 | 5.7 | Ω | f = 1 MHz | 2 |
| Turn-On Delay Time | td(on) | | 9 | 14 | ns | VDD = 30 V, RL = 7.5 Ω, ID ≅ 4 A, VGEN = 10 V, Rg = 1 Ω | 2 |
| Rise Time | tr | | 3 | 18 | ns | VDD = 30 V, RL = 7.5 Ω, ID ≅ 4 A, VGEN = 10 V, Rg = 1 Ω | 2 |
| Turn-Off Delay Time | td(off) | | 19 | 29 | ns | VDD = 30 V, RL = 7.5 Ω, ID ≅ 4 A, VGEN = 10 V, Rg = 1 Ω | 2 |
| Fall Time | tf | | 4 | 11 | ns | VDD = 30 V, RL = 7.5 Ω, ID ≅ 4 A, VGEN = 10 V, Rg = 1 Ω | 2 |
| Pulsed current (diode) | ISM | | | 29 | A | | 2 |
| Forward voltage | VSD | | 0.77 | 1.2 | V | IF = 1.6 A, VGS = 0 V | 2 |
| Body diode reverse recovery time | trr | | 19 | 38 | ns | IF = 4 A, di/dt = 100 A/μs | 2 |
| Body diode reverse recovery charge | Qrr | | 18 | 36 | nC | IF = 4 A, di/dt = 100 A/μs | 2 |
| Reverse recovery fall time | ta | | 15 | | ns | IF = 4 A, di/dt = 100 A/μs | 2 |
| Reverse recovery rise time | tb | | 4 | | ns | IF = 4 A, di/dt = 100 A/μs | 2 |
| Body diode peak reverse recovery current | IRM(REC) | | -2.1 | | A | IF = 4 A, di/dt = 100 A/μs | 2 |
## CAD (KiCad official)
- Symbol: `SQ3426CEV-T1_GE3`
- Footprint: `Package_SO:TSOP-6_1.65x3.05mm_P0.95mm`
- 3D model: TSOP-6 (KiCad packages3D, STEP)
- 3D model files: `sq3426cev-t1-ge3-etched.step` / `sq3426cev-t1-ge3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sq3426cev-t1-ge3.step` / `sq3426cev-t1-ge3.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Vishay Intertech datasheet](docs/sq3426cev-t1-ge3-datasheet.pdf) (9 pp, sha256 `952d69cf336454e7`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sq3426cev-t1-ge3-datasheet.pdf)